1 package era.mi.logic.components.gates;
3 import era.mi.logic.types.BitVector.BitVectorMutator;
4 import era.mi.logic.wires.Wire.ReadEnd;
5 import era.mi.logic.wires.Wire.ReadWriteEnd;
7 public class AndGate extends MultiInputGate
9 public AndGate(int processTime, ReadWriteEnd out, ReadEnd... in)
11 super(processTime, BitVectorMutator::and, out, in);