Output.java

   1 package net.mograsim.logic.model.verilog.model.signals;
   2
   3 public class Output extends IOPort
   4 {
   5         public Output(String name, int width)
   6         {
   7                 super(Type.IO_OUTPUT, name, width);
   8         }
   9
  10         @Override
  11         public String toDeclarationVerilogCode()
  12         {
  13                 return "output [" + (getWidth() - 1) + ":0] " + getName();
  14         }
  15 }