1 package net.mograsim.machine.standard.memory;
5 import net.mograsim.logic.core.components.BasicCoreComponent;
6 import net.mograsim.logic.core.timeline.Timeline;
7 import net.mograsim.logic.core.timeline.TimelineEventHandler;
8 import net.mograsim.logic.core.types.Bit;
9 import net.mograsim.logic.core.types.BitVector;
10 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
11 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
12 import net.mograsim.machine.MainMemoryDefinition;
15 * A memory component that only allows access to words of a specific width
17 public class WordAddressableMemoryComponent extends BasicCoreComponent
19 private final WordAddressableMemory memory;
20 private final static Bit read = Bit.ONE;
22 private ReadWriteEnd data;
23 private ReadEnd rWBit, address;
26 * @param data The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
28 * @param rWBit The value of the 0th bit dictates the mode: 0: Write, 1: Read
29 * @param address The bits of this ReadEnd address the memory cell to read/write
31 public WordAddressableMemoryComponent(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
32 ReadEnd rWBit, ReadEnd address)
34 super(timeline, processTime);
35 if(data.width() != definition.getCellWidth())
36 throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
37 if(rWBit.width() != 1)
38 throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
39 if(address.width() != definition.getMemoryAddressBits())
40 throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
43 this.address = address;
44 data.registerObserver(this);
45 rWBit.registerObserver(this);
46 address.registerObserver(this);
48 memory = new WordAddressableMemory(definition);
52 protected TimelineEventHandler compute()
54 if (!address.hasNumericValue())
56 if (read.equals(rWBit.getValue()))
57 return e -> data.feedSignals(Bit.U.toVector(data.width()));
58 return e -> data.clearSignals();
60 long addressed = address.getUnsignedValue();
61 if (read.equals(rWBit.getValue()))
63 BitVector storedData = memory.getCell(addressed);
64 return e -> data.feedSignals(storedData);
68 BitVector transData = data.getValues();
72 memory.setCell(addressed, transData);
78 public List<ReadEnd> getAllInputs()
80 return List.of(data, rWBit, address);
84 public List<ReadWriteEnd> getAllOutputs()