1 package net.mograsim.logic.model.verilog.converter;
3 import java.util.Objects;
6 import net.mograsim.logic.model.verilog.model.IOPort;
7 import net.mograsim.logic.model.verilog.model.Signal;
9 public class VerilogEmulatedModelPin
11 private final IOPort verilogPort;
12 private final int portIndex;
13 private final Set<PinNameBit> pinbits;
14 private final Type type;
16 public VerilogEmulatedModelPin(IOPort verilogPort, int portIndex, Set<PinNameBit> pinbits, Type type)
18 this.verilogPort = Objects.requireNonNull(verilogPort);
19 this.portIndex = portIndex;
20 this.pinbits = Set.copyOf(pinbits);
21 this.type = Objects.requireNonNull(type);
28 if (verilogPort.getWidth() != 2)
29 throw new IllegalArgumentException("Every Verilog port has to have width 2");
31 throw new IllegalArgumentException("Negative port index can't be negative");
35 if (verilogPort.getType() != Signal.Type.IO_INPUT)
36 throw new IllegalArgumentException("A PRE pin has to be an input");
39 if (verilogPort.getType() != Signal.Type.IO_OUTPUT)
40 throw new IllegalArgumentException("A OUT pin has to be an output");
43 if (verilogPort.getType() != Signal.Type.IO_INPUT)
44 throw new IllegalArgumentException("A RES pin has to be an input");
47 throw new IllegalStateException("Unknown enum constant: " + type);
51 public IOPort getVerilogPort()
56 public int getPortIndex()
61 public Set<PinNameBit> getPinbits()
76 result = prime * result + ((pinbits == null) ? 0 : pinbits.hashCode());
77 result = prime * result + portIndex;
78 result = prime * result + ((type == null) ? 0 : type.hashCode());
79 result = prime * result + ((verilogPort == null) ? 0 : verilogPort.hashCode());
84 public boolean equals(Object obj)
90 if (getClass() != obj.getClass())
92 VerilogEmulatedModelPin other = (VerilogEmulatedModelPin) obj;
95 if (other.pinbits != null)
97 } else if (!pinbits.equals(other.pinbits))
99 if (portIndex != other.portIndex)
101 if (type != other.type)
103 if (verilogPort == null)
105 if (other.verilogPort != null)
107 } else if (!verilogPort.equals(other.verilogPort))
112 public static enum Type