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   1 package net.mograsim.machine.standard.memory;
   2
   3 import java.util.List;
   4
   5 import net.mograsim.logic.core.components.BasicCoreComponent;
   6 import net.mograsim.logic.core.timeline.Timeline;
   7 import net.mograsim.logic.core.timeline.TimelineEventHandler;
   8 import net.mograsim.logic.core.types.Bit;
   9 import net.mograsim.logic.core.types.BitVector;
  10 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
  11 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
  12 import net.mograsim.machine.MainMemory;
  13 import net.mograsim.machine.MainMemoryDefinition;
  14
  15 /**
  16  * A memory component that only allows access to words of a specific width
  17  */
  18 public class CoreWordAddressableMemory extends BasicCoreComponent
  19 {
  20         private final MainMemory memory;
  21         private final static Bit read = Bit.ONE;
  22
  23         private ReadWriteEnd data;
  24         private ReadEnd rWBit, address;
  25
  26         /**
  27          * @param data    The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
  28          *                a memory word
  29          * @param rWBit   The value of the 0th bit dictates the mode: 0: Write, 1: Read
  30          * @param address The bits of this ReadEnd address the memory cell to read/write
  31          */
  32         public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data, ReadEnd rWBit,
  33                         ReadEnd address)
  34         {
  35                 super(timeline, processTime);
  36                 MainMemoryDefinition definition = memory.getDefinition();
  37                 if (data.width() != definition.getCellWidth())
  38                         throw new IllegalArgumentException(
  39                                         String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d",
  40                                                         definition.getCellWidth(), data.width()));
  41                 if (rWBit.width() != 1)
  42                         throw new IllegalArgumentException(
  43                                         String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
  44                 if (address.width() != definition.getMemoryAddressBits())
  45                         throw new IllegalArgumentException(
  46                                         String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d",
  47                                                         definition.getMemoryAddressBits(), address.width()));
  48                 this.memory = memory;
  49                 this.data = data;
  50                 this.rWBit = rWBit;
  51                 this.address = address;
  52                 memory.registerObserver(a -> update());
  53                 data.registerObserver(this);
  54                 rWBit.registerObserver(this);
  55                 address.registerObserver(this);
  56         }
  57
  58         @Override
  59         protected TimelineEventHandler compute()
  60         {
  61                 if (!address.getValues().isBinary())
  62                 {
  63                         if (read.equals(rWBit.getValue()))
  64                                 return e -> data.feedSignals(Bit.U.toVector(data.width()));// TODO don't always feed U, but decide to feed X or U.
  65                         return e -> data.clearSignals();
  66                 }
  67                 long addressed = address.getValues().getUnsignedValueLong();
  68                 if (read.equals(rWBit.getValue()))
  69                 {
  70                         BitVector storedData = memory.getCell(addressed);
  71                         return e -> data.feedSignals(storedData);
  72                 }
  73                 BitVector transData = data.getValues();
  74                 boolean isNewData = !transData.equals(memory.getCell(addressed));
  75                 return e ->
  76                 {
  77                         data.clearSignals();
  78                         if (isNewData)
  79                                 memory.setCell(addressed, transData);
  80                 };
  81         }
  82
  83         @Override
  84         public List<ReadEnd> getAllInputs()
  85         {
  86                 return List.of(data, rWBit, address);
  87         }
  88
  89         @Override
  90         public List<ReadWriteEnd> getAllOutputs()
  91         {
  92                 return List.of(data);
  93         }
  94 }