90cfcc7ee7d5939a0e90e57a2ff2d0b3d670ba70
[Mograsim.git] /
1 {
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153     ],
154     "wires": [
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159         },
160         "pin2": {
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183         },
184         "pin2": {
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195         },
196         "pin2": {
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257           "pinName": ""
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276         "pin2": {
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291           "pinName": ""
292         },
293         "pin2": {
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295           "pinName": "B"
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302           }
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305       {
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308           "pinName": ""
309         },
310         "pin2": {
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312           "pinName": "B"
313         },
314         "name": "unnamedWire#10",
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319           }
320         ]
321       },
322       {
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325           "pinName": ""
326         },
327         "pin2": {
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329           "pinName": "B"
330         },
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342           "pinName": "Y"
343         },
344         "pin2": {
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346           "pinName": "Y1"
347         },
348         "name": "unnamedWire#12",
349         "path": []
350       },
351       {
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354           "pinName": "Y"
355         },
356         "pin2": {
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358           "pinName": "Y2"
359         },
360         "name": "unnamedWire#13",
361         "path": []
362       },
363       {
364         "pin1": {
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366           "pinName": "Y"
367         },
368         "pin2": {
369           "compName": "_submodelinterface",
370           "pinName": "Y3"
371         },
372         "name": "unnamedWire#14",
373         "path": []
374       },
375       {
376         "pin1": {
377           "compName": "NandGate#3",
378           "pinName": "Y"
379         },
380         "pin2": {
381           "compName": "_submodelinterface",
382           "pinName": "Y4"
383         },
384         "name": "unnamedWire#15",
385         "path": []
386       }
387     ],
388     "version": "0.1.1"
389   },
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396     "pinLabelMargin": 0.5
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398   "outlineRendererSnippetID": "default",
399   "highLevelStateHandlerSnippetID": "default",
400   "version": "0.1.5"
401 }