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   1 package net.mograsim.logic.model.verilog.model.signals;
   2
   3 public class Wire extends NamedSignal
   4 {
   5         public Wire(String name, int width)
   6         {
   7                 super(Type.WIRE, name, width);
   8         }
   9
  10         public String toDeclarationVerilogCode()
  11         {
  12                 return "wire [" + getWidth() + ":0] " + getName() + ";";
  13         }
  14 }