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   1 package net.mograsim.logic.model.verilog.model.signals;
   2
   3 import java.util.Objects;
   4
   5 public abstract class Signal
   6 {
   7         private final Type type;
   8         private final int width;
   9
  10         public Signal(Type type, int width)
  11         {
  12                 this.type = Objects.requireNonNull(type);
  13                 this.width = width;
  14
  15                 check();
  16         }
  17
  18         private void check()
  19         {
  20                 if (width <= 0)
  21                         throw new IllegalArgumentException("Signal width is negative: " + width);
  22         }
  23
  24         public Type getType()
  25         {
  26                 return type;
  27         }
  28
  29         public int getWidth()
  30         {
  31                 return width;
  32         }
  33
  34         public abstract String toReferenceVerilogCode();
  35
  36         @Override
  37         public int hashCode()
  38         {
  39                 final int prime = 31;
  40                 int result = 1;
  41                 result = prime * result + ((type == null) ? 0 : type.hashCode());
  42                 result = prime * result + width;
  43                 return result;
  44         }
  45
  46         @Override
  47         public boolean equals(Object obj)
  48         {
  49                 if (this == obj)
  50                         return true;
  51                 if (obj == null)
  52                         return false;
  53                 if (getClass() != obj.getClass())
  54                         return false;
  55                 Signal other = (Signal) obj;
  56                 if (type != other.type)
  57                         return false;
  58                 if (width != other.width)
  59                         return false;
  60                 return true;
  61         }
  62
  63         public static enum Type
  64         {
  65                 WIRE, IO_INPUT, IO_OUTPUT, CONSTANT;
  66         }
  67 }