X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=era.mi%2Fsrc%2Fera%2Fmi%2Flogic%2Ftests%2FComponentTest.java;h=2da847e3e49756a3762900a7125de7527818f757;hb=b7ce41467a2cbd9f45554982730741810e99feaa;hp=398c18fe30f07e90f2e305004e9bf0e848dc756f;hpb=c1d0ddc342c482051fa6c455bb286617135bd3c3;p=Mograsim.git diff --git a/era.mi/src/era/mi/logic/tests/ComponentTest.java b/era.mi/src/era/mi/logic/tests/ComponentTest.java index 398c18fe..2da847e3 100644 --- a/era.mi/src/era/mi/logic/tests/ComponentTest.java +++ b/era.mi/src/era/mi/logic/tests/ComponentTest.java @@ -1,14 +1,15 @@ package era.mi.logic.tests; -import static org.junit.jupiter.api.Assertions.*; +import static org.junit.jupiter.api.Assertions.assertArrayEquals; +import static org.junit.jupiter.api.Assertions.assertEquals; +import static org.junit.jupiter.api.Assertions.fail; -import java.util.Arrays; import java.util.function.LongConsumer; import org.junit.jupiter.api.Test; -import era.mi.logic.Bit; import era.mi.logic.Simulation; +import era.mi.logic.components.Connector; import era.mi.logic.components.Demux; import era.mi.logic.components.Merger; import era.mi.logic.components.Mux; @@ -18,8 +19,11 @@ import era.mi.logic.components.gates.AndGate; import era.mi.logic.components.gates.NotGate; import era.mi.logic.components.gates.OrGate; import era.mi.logic.components.gates.XorGate; +import era.mi.logic.types.Bit; +import era.mi.logic.types.BitVector; import era.mi.logic.wires.Wire; -import era.mi.logic.wires.Wire.WireEnd; +import era.mi.logic.wires.Wire.ReadEnd; +import era.mi.logic.wires.Wire.ReadWriteEnd; class ComponentTest { @@ -28,14 +32,13 @@ class ComponentTest void circuitExampleTest() { Simulation.TIMELINE.reset(); - Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1), - e = new Wire(1, 1), f = new Wire(1, 1), g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1), - j = new Wire(1, 1), k = new Wire(1, 1); - new AndGate(1, f.createEnd(), a.createEnd(), b.createEnd()); - new NotGate(1, f.createEnd(), g.createEnd()); - new Merger(h.createEnd(), c.createEnd(), g.createEnd()); - new Mux(1, i.createEnd(), e.createEnd(), h.createEnd(), d.createEnd()); - new Splitter(i.createEnd(), k.createEnd(), j.createEnd()); + Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1), e = new Wire(1, 1), f = new Wire(1, 1), + g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1), j = new Wire(1, 1), k = new Wire(1, 1); + new AndGate(1, f.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); + new NotGate(1, f.createReadOnlyEnd(), g.createEnd()); + new Merger(h.createEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd()); + new Mux(1, i.createEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd()); + new Splitter(i.createReadOnlyEnd(), k.createEnd(), j.createEnd()); a.createEnd().feedSignals(Bit.ZERO); b.createEnd().feedSignals(Bit.ONE); @@ -55,7 +58,7 @@ class ComponentTest Simulation.TIMELINE.reset(); Wire a = new Wire(3, 1), b = new Wire(2, 1), c = new Wire(3, 1), in = new Wire(8, 1); in.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); - new Splitter(in.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new Splitter(in.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd()); Simulation.TIMELINE.executeAll(); @@ -73,25 +76,25 @@ class ComponentTest b.createEnd().feedSignals(Bit.ONE, Bit.ZERO); c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); - new Merger(out.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new Merger(out.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); Simulation.TIMELINE.executeAll(); - assertTrue( - Arrays.equals(out.getValues(), new Bit[] { Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE })); + assertBitArrayEquals(out.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); } @Test void triStateBufferTest() { Wire a = new Wire(1, 1), b = new Wire(1, 1), en = new Wire(1, 1), notEn = new Wire(1, 1); - new NotGate(1, en.createEnd(), notEn.createEnd()); - new TriStateBuffer(1, a.createEnd(), b.createEnd(), en.createEnd()); - new TriStateBuffer(1, b.createEnd(), a.createEnd(), notEn.createEnd()); + new NotGate(1, en.createReadOnlyEnd(), notEn.createEnd()); + new TriStateBuffer(1, a.createReadOnlyEnd(), b.createEnd(), en.createReadOnlyEnd()); + new TriStateBuffer(1, b.createReadOnlyEnd(), a.createEnd(), notEn.createReadOnlyEnd()); - WireEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd(); + ReadWriteEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd(); enI.feedSignals(Bit.ONE); aI.feedSignals(Bit.ONE); + bI.feedSignals(Bit.Z); Simulation.TIMELINE.executeAll(); @@ -117,15 +120,14 @@ class ComponentTest void muxTest() { Simulation.TIMELINE.reset(); - Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), - out = new Wire(4, 1); - WireEnd selectIn = select.createEnd(); + Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), out = new Wire(4, 1); + ReadWriteEnd selectIn = select.createEnd(); selectIn.feedSignals(Bit.ZERO, Bit.ZERO); a.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); c.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); - new Mux(1, out.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new Mux(1, out.createEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); Simulation.TIMELINE.executeAll(); assertBitArrayEquals(out.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); @@ -145,14 +147,13 @@ class ComponentTest void demuxTest() { Simulation.TIMELINE.reset(); - Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), - in = new Wire(4, 1); - WireEnd selectIn = select.createEnd(); + Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), in = new Wire(4, 1); + ReadWriteEnd selectIn = select.createEnd(); selectIn.feedSignals(Bit.ZERO, Bit.ZERO); in.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); - new Demux(1, in.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new Demux(1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd()); Simulation.TIMELINE.executeAll(); assertBitArrayEquals(a.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); @@ -179,7 +180,7 @@ class ComponentTest { Simulation.TIMELINE.reset(); Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1); - new AndGate(1, c.createEnd(), a.createEnd(), b.createEnd()); + new AndGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); @@ -193,7 +194,7 @@ class ComponentTest { Simulation.TIMELINE.reset(); Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1); - new OrGate(1, c.createEnd(), a.createEnd(), b.createEnd()); + new OrGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); @@ -207,7 +208,7 @@ class ComponentTest { Simulation.TIMELINE.reset(); Wire a = new Wire(3, 1), b = new Wire(3, 2), c = new Wire(3, 1), d = new Wire(3, 1); - new XorGate(1, d.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new XorGate(1, d.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE); b.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); @@ -216,13 +217,13 @@ class ComponentTest assertBitArrayEquals(d.getValues(), Bit.ZERO, Bit.ONE, Bit.ONE); } - + @Test void notTest() { Simulation.TIMELINE.reset(); Wire a = new Wire(3, 1), b = new Wire(3, 2); - new NotGate(1, a.createEnd(), b.createEnd()); + new NotGate(1, a.createReadOnlyEnd(), b.createEnd()); a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE); Simulation.TIMELINE.executeAll(); @@ -234,15 +235,14 @@ class ComponentTest void rsLatchCircuitTest() { Simulation.TIMELINE.reset(); - Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1), - q = new Wire(1, 1), nq = new Wire(1, 1); + Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1), q = new Wire(1, 1), nq = new Wire(1, 1); - new OrGate(1, t2.createEnd(), r.createEnd(), nq.createEnd()); - new OrGate(1, t1.createEnd(), s.createEnd(), q.createEnd()); - new NotGate(1, t2.createEnd(), q.createEnd()); - new NotGate(1, t1.createEnd(), nq.createEnd()); + new OrGate(1, t2.createEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd()); + new OrGate(1, t1.createEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd()); + new NotGate(1, t2.createReadOnlyEnd(), q.createEnd()); + new NotGate(1, t1.createReadOnlyEnd(), nq.createEnd()); - WireEnd sIn = s.createEnd(), rIn = r.createEnd(); + ReadWriteEnd sIn = s.createEnd(), rIn = r.createEnd(); sIn.feedSignals(Bit.ONE); rIn.feedSignals(Bit.ZERO); @@ -285,7 +285,7 @@ class ComponentTest { Simulation.TIMELINE.reset(); Wire w = new Wire(2, 1); - WireEnd wI1 = w.createEnd(), wI2 = w.createEnd(); + ReadWriteEnd wI1 = w.createEnd(), wI2 = w.createEnd(); wI1.feedSignals(Bit.ONE, Bit.Z); wI2.feedSignals(Bit.Z, Bit.X); Simulation.TIMELINE.executeAll(); @@ -300,12 +300,18 @@ class ComponentTest assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z); wI2.feedSignals(Bit.ONE, Bit.Z); - w.addObserver((i, oldValues) -> fail("WireArray notified observer, although value did not change.")); + ReadEnd rE = w.createReadOnlyEnd(); + rE.addObserver((i, oldValues) -> fail("WireEnd notified observer, although value did not change.")); Simulation.TIMELINE.executeAll(); + rE.close(); + wI1.feedSignals(Bit.X, Bit.X); + Simulation.TIMELINE.executeAll(); + wI1.addObserver((i, oldValues) -> fail("WireEnd notified observer, although it was closed.")); + wI1.close(); assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z); } -// @Test + @Test void wireConnections() { // Nur ein Experiment, was über mehrere 'passive' Bausteine hinweg passieren würde @@ -315,12 +321,12 @@ class ComponentTest Wire a = new Wire(1, 2); Wire b = new Wire(1, 2); Wire c = new Wire(1, 2); - WireEnd aI = a.createEnd(); - WireEnd bI = b.createEnd(); - WireEnd cI = c.createEnd(); + ReadWriteEnd aI = a.createEnd(); + ReadWriteEnd bI = b.createEnd(); + ReadWriteEnd cI = c.createEnd(); - TestBitDisplay test = new TestBitDisplay(c.createEnd()); - TestBitDisplay test2 = new TestBitDisplay(a.createEnd()); + TestBitDisplay test = new TestBitDisplay(c.createReadOnlyEnd()); + TestBitDisplay test2 = new TestBitDisplay(a.createReadOnlyEnd()); LongConsumer print = time -> System.out.format("Time %2d\n a: %s\n b: %s\n c: %s\n", time, a, b, c); cI.feedSignals(Bit.ONE); @@ -333,7 +339,7 @@ class ComponentTest cI.feedSignals(Bit.Z); test.assertAfterSimulationIs(print, Bit.Z); - new Connector(b, c); + new Connector(b.createEnd(), c.createEnd()).connect(); test.assertAfterSimulationIs(print, Bit.Z); System.err.println("ONE"); bI.feedSignals(Bit.ONE); @@ -345,7 +351,7 @@ class ComponentTest bI.feedSignals(Bit.Z); test.assertAfterSimulationIs(print, Bit.Z); - new Connector(a, b); + new Connector(a.createEnd(), b.createEnd()).connect(); System.err.println("Z 2"); aI.feedSignals(Bit.Z); test.assertAfterSimulationIs(print, Bit.Z); @@ -379,8 +385,8 @@ class ComponentTest test2.assertAfterSimulationIs(Bit.ONE); } - private static void assertBitArrayEquals(Bit[] actual, Bit... expected) + private static void assertBitArrayEquals(BitVector actual, Bit... expected) { - assertArrayEquals(expected, actual); + assertArrayEquals(expected, actual.getBits()); } }