X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=era.mi%2Fsrc%2Fera%2Fmi%2Flogic%2Ftests%2FComponentTest.java;h=cb2195edae4a438b7f1c59fcd1d9fd79bb13511a;hb=dcbba0b189fd37135adc4487f1b8b645e7045bc4;hp=c14fd01da2e49db0c16cba65c72e80a644beda53;hpb=b1e7855af2dfc15b4d6c1253dd77db02925162f3;p=Mograsim.git diff --git a/era.mi/src/era/mi/logic/tests/ComponentTest.java b/era.mi/src/era/mi/logic/tests/ComponentTest.java index c14fd01d..cb2195ed 100644 --- a/era.mi/src/era/mi/logic/tests/ComponentTest.java +++ b/era.mi/src/era/mi/logic/tests/ComponentTest.java @@ -1,16 +1,12 @@ package era.mi.logic.tests; -import static org.junit.jupiter.api.Assertions.assertArrayEquals; -import static org.junit.jupiter.api.Assertions.assertEquals; -import static org.junit.jupiter.api.Assertions.assertTrue; -import static org.junit.jupiter.api.Assertions.fail; +import static org.junit.jupiter.api.Assertions.*; import java.util.Arrays; import java.util.function.LongConsumer; import org.junit.jupiter.api.Test; -import era.mi.logic.Bit; import era.mi.logic.Simulation; import era.mi.logic.components.Connector; import era.mi.logic.components.Demux; @@ -22,6 +18,7 @@ import era.mi.logic.components.gates.AndGate; import era.mi.logic.components.gates.NotGate; import era.mi.logic.components.gates.OrGate; import era.mi.logic.components.gates.XorGate; +import era.mi.logic.types.Bit; import era.mi.logic.wires.Wire; import era.mi.logic.wires.Wire.WireEnd; @@ -35,11 +32,11 @@ class ComponentTest Simulation.TIMELINE.reset(); Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1), e = new Wire(1, 1), f = new Wire(1, 1), g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1), j = new Wire(1, 1), k = new Wire(1, 1); - new AndGate(1, f.createEnd(), a.createEnd(), b.createEnd()); - new NotGate(1, f.createEnd(), g.createEnd()); - new Merger(h.createEnd(), c.createEnd(), g.createEnd()); - new Mux(1, i.createEnd(), e.createEnd(), h.createEnd(), d.createEnd()); - new Splitter(i.createEnd(), k.createEnd(), j.createEnd()); + new AndGate(1, f.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); + new NotGate(1, f.createReadOnlyEnd(), g.createEnd()); + new Merger(h.createEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd()); + new Mux(1, i.createEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd()); + new Splitter(i.createReadOnlyEnd(), k.createEnd(), j.createEnd()); a.createEnd().feedSignals(Bit.ZERO); b.createEnd().feedSignals(Bit.ONE); @@ -59,7 +56,7 @@ class ComponentTest Simulation.TIMELINE.reset(); Wire a = new Wire(3, 1), b = new Wire(2, 1), c = new Wire(3, 1), in = new Wire(8, 1); in.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); - new Splitter(in.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new Splitter(in.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd()); Simulation.TIMELINE.executeAll(); @@ -77,7 +74,7 @@ class ComponentTest b.createEnd().feedSignals(Bit.ONE, Bit.ZERO); c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); - new Merger(out.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new Merger(out.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); Simulation.TIMELINE.executeAll(); @@ -89,9 +86,9 @@ class ComponentTest void triStateBufferTest() { Wire a = new Wire(1, 1), b = new Wire(1, 1), en = new Wire(1, 1), notEn = new Wire(1, 1); - new NotGate(1, en.createEnd(), notEn.createEnd()); - new TriStateBuffer(1, a.createEnd(), b.createEnd(), en.createEnd()); - new TriStateBuffer(1, b.createEnd(), a.createEnd(), notEn.createEnd()); + new NotGate(1, en.createReadOnlyEnd(), notEn.createEnd()); + new TriStateBuffer(1, a.createReadOnlyEnd(), b.createEnd(), en.createReadOnlyEnd()); + new TriStateBuffer(1, b.createReadOnlyEnd(), a.createEnd(), notEn.createReadOnlyEnd()); WireEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd(); enI.feedSignals(Bit.ONE); @@ -129,7 +126,7 @@ class ComponentTest a.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); c.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); - new Mux(1, out.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new Mux(1, out.createEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); Simulation.TIMELINE.executeAll(); assertBitArrayEquals(out.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); @@ -155,7 +152,7 @@ class ComponentTest selectIn.feedSignals(Bit.ZERO, Bit.ZERO); in.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); - new Demux(1, in.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new Demux(1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd()); Simulation.TIMELINE.executeAll(); assertBitArrayEquals(a.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); @@ -182,7 +179,7 @@ class ComponentTest { Simulation.TIMELINE.reset(); Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1); - new AndGate(1, c.createEnd(), a.createEnd(), b.createEnd()); + new AndGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); @@ -196,7 +193,7 @@ class ComponentTest { Simulation.TIMELINE.reset(); Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1); - new OrGate(1, c.createEnd(), a.createEnd(), b.createEnd()); + new OrGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); @@ -210,7 +207,7 @@ class ComponentTest { Simulation.TIMELINE.reset(); Wire a = new Wire(3, 1), b = new Wire(3, 2), c = new Wire(3, 1), d = new Wire(3, 1); - new XorGate(1, d.createEnd(), a.createEnd(), b.createEnd(), c.createEnd()); + new XorGate(1, d.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE); b.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); @@ -225,7 +222,7 @@ class ComponentTest { Simulation.TIMELINE.reset(); Wire a = new Wire(3, 1), b = new Wire(3, 2); - new NotGate(1, a.createEnd(), b.createEnd()); + new NotGate(1, a.createReadOnlyEnd(), b.createEnd()); a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE); Simulation.TIMELINE.executeAll(); @@ -239,10 +236,10 @@ class ComponentTest Simulation.TIMELINE.reset(); Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1), q = new Wire(1, 1), nq = new Wire(1, 1); - new OrGate(1, t2.createEnd(), r.createEnd(), nq.createEnd()); - new OrGate(1, t1.createEnd(), s.createEnd(), q.createEnd()); - new NotGate(1, t2.createEnd(), q.createEnd()); - new NotGate(1, t1.createEnd(), nq.createEnd()); + new OrGate(1, t2.createEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd()); + new OrGate(1, t1.createEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd()); + new NotGate(1, t2.createReadOnlyEnd(), q.createEnd()); + new NotGate(1, t1.createReadOnlyEnd(), nq.createEnd()); WireEnd sIn = s.createEnd(), rIn = r.createEnd(); @@ -321,8 +318,8 @@ class ComponentTest WireEnd bI = b.createEnd(); WireEnd cI = c.createEnd(); - TestBitDisplay test = new TestBitDisplay(c.createEnd()); - TestBitDisplay test2 = new TestBitDisplay(a.createEnd()); + TestBitDisplay test = new TestBitDisplay(c.createReadOnlyEnd()); + TestBitDisplay test2 = new TestBitDisplay(a.createReadOnlyEnd()); LongConsumer print = time -> System.out.format("Time %2d\n a: %s\n b: %s\n c: %s\n", time, a, b, c); cI.feedSignals(Bit.ONE);