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diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalSplitter.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalSplitter.java
new file mode 100644
index 00000000..d77e1541
--- /dev/null
+++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalSplitter.java
@@ -0,0 +1,60 @@
+package net.mograsim.logic.core.components;
+
+import java.util.List;
+
+import net.mograsim.logic.core.LogicObservable;
+import net.mograsim.logic.core.LogicObserver;
+import net.mograsim.logic.core.timeline.Timeline;
+import net.mograsim.logic.core.types.BitVector;
+import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
+import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
+
+public class CoreUnidirectionalSplitter extends CoreComponent implements LogicObserver
+{
+	private ReadEnd input;
+	private ReadWriteEnd[] outputs;
+
+	public CoreUnidirectionalSplitter(Timeline timeline, ReadEnd input, ReadWriteEnd... outputs)
+	{
+		super(timeline);
+		this.input = input;
+		this.outputs = outputs;
+		input.registerObserver(this);
+		int width = 0;
+		for (ReadEnd out : outputs)
+			width += out.width();
+
+		if (input.width() != width)
+			throw new IllegalArgumentException(
+					"The input of splitting one into n WireArrays must have width = a1.width() + a2.width() + ... + an.width().");
+	}
+
+	protected void compute()
+	{
+		BitVector inputBits = input.getValues();
+		int startIndex = 0;
+		for (int i = 0; i < outputs.length; i++)
+		{
+			outputs[i].feedSignals(inputBits.subVector(startIndex, startIndex + outputs[i].width()));
+			startIndex += outputs[i].width();
+		}
+	}
+
+	@Override
+	public void update(LogicObservable initiator)
+	{
+		compute();
+	}
+
+	@Override
+	public List<ReadEnd> getAllInputs()
+	{
+		return List.of(input);
+	}
+
+	@Override
+	public List<ReadWriteEnd> getAllOutputs()
+	{
+		return List.of(outputs);
+	}
+}