X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=net.mograsim.logic.core%2Ftest%2Fnet%2Fmograsim%2Flogic%2Fcore%2Ftests%2FComponentTest.java;h=d69cd009aa2aaaafcfeb6132898d42b99cedc4fd;hb=3e6ac3d7fd389191d02c1c6982fbf093421ce4f2;hp=6055296f8cedbde2e09a61527ca9f6c547d18483;hpb=452b5630f12a4ffa8b15012980f2e6b8469c571b;p=Mograsim.git

diff --git a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/ComponentTest.java b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/ComponentTest.java
index 6055296f..d69cd009 100644
--- a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/ComponentTest.java
+++ b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/ComponentTest.java
@@ -23,7 +23,6 @@ import net.mograsim.logic.core.components.gates.NorGate;
 import net.mograsim.logic.core.components.gates.NotGate;
 import net.mograsim.logic.core.components.gates.OrGate;
 import net.mograsim.logic.core.components.gates.XorGate;
-import net.mograsim.logic.core.components.memory.WordAddressableMemoryComponent;
 import net.mograsim.logic.core.timeline.Timeline;
 import net.mograsim.logic.core.types.Bit;
 import net.mograsim.logic.core.types.BitVector;
@@ -99,9 +98,9 @@ class ComponentTest
 	void fusionTest1()
 	{
 		Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), out = new Wire(t, 8, 1);
-		Wire.fuse(a, out, 0, 0, a.length);
-		Wire.fuse(b, out, 0, a.length, b.length);
-		Wire.fuse(c, out, 0, a.length + b.length, c.length);
+		Wire.fuse(a, out, 0, 0, a.width);
+		Wire.fuse(b, out, 0, a.width, b.width);
+		Wire.fuse(c, out, 0, a.width + b.width, c.width);
 		ReadWriteEnd rA = a.createReadWriteEnd();
 		rA.feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO);
 		ReadWriteEnd rB = b.createReadWriteEnd();
@@ -519,47 +518,6 @@ class ComponentTest
 		test2.assertAfterSimulationIs(Bit.ONE);
 	}
 
-	@Test
-	public void wordAddressableMemoryLargeTest()
-	{
-		Wire rW = new Wire(t, 1, 2);
-		Wire data = new Wire(t, 16, 2);
-		Wire address = new Wire(t, 64, 2);
-		ReadWriteEnd rWI = rW.createReadWriteEnd();
-		ReadWriteEnd dataI = data.createReadWriteEnd();
-		ReadWriteEnd addressI = address.createReadWriteEnd();
-
-		WordAddressableMemoryComponent memory = new WordAddressableMemoryComponent(t, 4, 4096L, Long.MAX_VALUE, data.createReadWriteEnd(),
-				rW.createReadOnlyEnd(), address.createReadOnlyEnd());
-
-		Random r = new Random();
-		for (long j = 1; j > 0; j *= 2)
-		{
-			for (int i = 0; i < 50; i++)
-			{
-				String sAddress = String.format("%64s", BigInteger.valueOf(4096 + i + j).toString(2)).replace(' ', '0');
-				sAddress = new StringBuilder(sAddress).reverse().toString();
-				BitVector bAddress = BitVector.parse(sAddress);
-				addressI.feedSignals(bAddress);
-				t.executeAll();
-				String random = BigInteger.valueOf(Math.abs(r.nextInt())).toString(5);
-				random = random.substring(Integer.max(0, random.length() - 16));
-				random = String.format("%16s", random).replace(' ', '0');
-				random = random.replace('2', 'X').replace('3', 'Z').replace('4', 'U');
-				BitVector vector = BitVector.parse(random);
-				dataI.feedSignals(vector);
-				rWI.feedSignals(Bit.ZERO);
-				t.executeAll();
-				rWI.feedSignals(Bit.ONE);
-				t.executeAll();
-				dataI.clearSignals();
-				t.executeAll();
-
-				assertBitArrayEquals(dataI.getValues(), vector.getBits());
-			}
-		}
-	}
-
 	private static void assertBitArrayEquals(BitVector actual, Bit... expected)
 	{
 		assertArrayEquals(expected, actual.getBits());