X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=net.mograsim.logic.model.am2900%2Fcomponents%2FGUI_rsLatch.json;fp=net.mograsim.logic.model.am2900%2Fcomponents%2FGUI_rsLatch.json;h=4199e45fcfa34f6ecae163ae25f4155fc7ecd045;hb=3977f16649531ca3ba345c9cd5ec365e0b804783;hp=f644070610b3e67448f233578a2580e3f55b9dbe;hpb=13e5f7aac4b3584b0f4b70c7894fb1667b22cb41;p=Mograsim.git diff --git a/net.mograsim.logic.model.am2900/components/GUI_rsLatch.json b/net.mograsim.logic.model.am2900/components/GUI_rsLatch.json index f6440706..4199e45f 100644 --- a/net.mograsim.logic.model.am2900/components/GUI_rsLatch.json +++ b/net.mograsim.logic.model.am2900/components/GUI_rsLatch.json @@ -77,18 +77,6 @@ mograsim version: 0.1.3 } ], "innerWires": [ - { - "pin1": { - "compName": "WireCrossPoint#1", - "pinName": "" - }, - "pin2": { - "compName": "_submodelinterface", - "pinName": "_Q" - }, - "name": "unnamedWire#7", - "path": [] - }, { "pin1": { "compName": "WireCrossPoint#0", @@ -98,7 +86,7 @@ mograsim version: 0.1.3 "compName": "_submodelinterface", "pinName": "Q" }, - "name": "unnamedWire#6", + "name": "q", "path": [ { "x": 35.0, @@ -118,6 +106,18 @@ mograsim version: 0.1.3 } ] }, + { + "pin1": { + "compName": "WireCrossPoint#1", + "pinName": "" + }, + "pin2": { + "compName": "_submodelinterface", + "pinName": "_Q" + }, + "name": "_q", + "path": [] + }, { "pin1": { "compName": "_submodelinterface", @@ -219,12 +219,30 @@ mograsim version: 0.1.3 } ] }, - "symbolRendererSnippetID": "simpleRectangularLike", + "symbolRendererSnippetID": "class:net.mograsim.logic.model.snippets.symbolrenderers.SimpleRectangularLikeSymbolRenderer", "symbolRendererParams": { "centerText": "_rsLatch", "centerTextHeight": 5.0, "horizontalComponentCenter": 17.5, "pinLabelHeight": 3.5, "pinLabelMargin": 0.5 + }, + "outlineRendererSnippetID": "class:net.mograsim.logic.model.snippets.outlinerenderers.DefaultOutlineRenderer", + "highLevelStateHandlerSnippetID": "class:net.mograsim.logic.model.snippets.highlevelstatehandlers.standard.StandardHighLevelStateHandler", + "highLevelStateHandlerParams": { + "subcomponentHighLevelStates": {}, + "atomicHighLevelStates": { + "q": { + "id": "class:net.mograsim.logic.model.snippets.highlevelstatehandlers.standard.atomic.WireForcingAtomicHighLevelStateHandler", + "params": { + "wiresToForce": [ + "q" + ], + "wiresToForceInverted": [ + "_q" + ] + } + } + } } } \ No newline at end of file