X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=net.mograsim.machine%2Fsrc%2Fnet%2Fmograsim%2Fmachine%2Fstandard%2Fmemory%2FCoreWordAddressableMemory.java;h=882b031ac194296e18b69fe3e9f43486dc1e14c5;hb=4ba119cab03498736851e6f3f32eec1957839a2e;hp=addb34cbbe44060e0d1ce195410911c4ba7eafd1;hpb=7b8035a065c7b64f38850907d519f9a7dfb67e24;p=Mograsim.git diff --git a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java index addb34cb..882b031a 100644 --- a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java +++ b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java @@ -21,7 +21,7 @@ public class CoreWordAddressableMemory extends BasicCoreComponent private final static Bit read = Bit.ONE; private ReadWriteEnd data; - private ReadEnd rWBit, address, clock; + private ReadEnd rWBit, address; /** * @param data The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of @@ -29,39 +29,39 @@ public class CoreWordAddressableMemory extends BasicCoreComponent * @param rWBit The value of the 0th bit dictates the mode: 0: Write, 1: Read * @param address The bits of this ReadEnd address the memory cell to read/write */ - public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data, - ReadEnd rWBit, ReadEnd address, ReadEnd clock) + public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data, ReadEnd rWBit, + ReadEnd address) { super(timeline, processTime); MainMemoryDefinition definition = memory.getDefinition(); - if(data.width() != definition.getCellWidth()) - throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width())); - if(rWBit.width() != 1) - throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width())); - if(address.width() != definition.getMemoryAddressBits()) - throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width())); + if (data.width() != definition.getCellWidth()) + throw new IllegalArgumentException( + String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", + definition.getCellWidth(), data.width())); + if (rWBit.width() != 1) + throw new IllegalArgumentException( + String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width())); + if (address.width() != definition.getMemoryAddressBits()) + throw new IllegalArgumentException( + String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", + definition.getMemoryAddressBits(), address.width())); this.data = data; this.rWBit = rWBit; this.address = address; - this.clock = clock; data.registerObserver(this); rWBit.registerObserver(this); address.registerObserver(this); - clock.registerObserver(this); - + this.memory = memory; } @Override protected TimelineEventHandler compute() { - if(clock.getValue() != Bit.ONE) - return null; - if (!address.hasNumericValue()) { if (read.equals(rWBit.getValue())) - return e -> data.feedSignals(Bit.U.toVector(data.width())); + return e -> data.feedSignals(Bit.U.toVector(data.width()));// TODO don't always feed U, but decide to feed X or U. return e -> data.clearSignals(); } long addressed = address.getUnsignedValue(); @@ -69,8 +69,7 @@ public class CoreWordAddressableMemory extends BasicCoreComponent { BitVector storedData = memory.getCell(addressed); return e -> data.feedSignals(storedData); - } - else + } else { BitVector transData = data.getValues(); return e ->