X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=net.mograsim.machine%2Fsrc%2Fnet%2Fmograsim%2Fmachine%2Fstandard%2Fmemory%2FCoreWordAddressableMemory.java;h=ca557a6b923ab982713c414483a90fecd9984c57;hb=8bed58cd47f4e53a0a83e066d38864aa6875502f;hp=afad26abd18cced11c4c6053d9a76f6a5a0030ec;hpb=88e1b4382640ee4e907e06572fe6794bc925f344;p=Mograsim.git diff --git a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java index afad26ab..ca557a6b 100644 --- a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java +++ b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java @@ -29,51 +29,55 @@ public class CoreWordAddressableMemory extends BasicCoreComponent * @param rWBit The value of the 0th bit dictates the mode: 0: Write, 1: Read * @param address The bits of this ReadEnd address the memory cell to read/write */ - public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data, - ReadEnd rWBit, ReadEnd address) + public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data, ReadEnd rWBit, + ReadEnd address) { super(timeline, processTime); MainMemoryDefinition definition = memory.getDefinition(); - if(data.width() != definition.getCellWidth()) - throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width())); - if(rWBit.width() != 1) - throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width())); - if(address.width() != definition.getMemoryAddressBits()) - throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width())); + if (data.width() != definition.getCellWidth()) + throw new IllegalArgumentException( + String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", + definition.getCellWidth(), data.width())); + if (rWBit.width() != 1) + throw new IllegalArgumentException( + String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width())); + if (address.width() != definition.getMemoryAddressBits()) + throw new IllegalArgumentException( + String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", + definition.getMemoryAddressBits(), address.width())); + this.memory = memory; this.data = data; this.rWBit = rWBit; this.address = address; + memory.registerObserver(a -> update()); data.registerObserver(this); rWBit.registerObserver(this); address.registerObserver(this); - - this.memory = memory; } @Override protected TimelineEventHandler compute() { - if (!address.hasNumericValue()) + if (!address.getValues().isBinary()) { if (read.equals(rWBit.getValue())) - return e -> data.feedSignals(Bit.U.toVector(data.width()));//TODO don't always feed U, but decide to feed X or U. + return e -> data.feedSignals(Bit.U.toVector(data.width()));// TODO don't always feed U, but decide to feed X or U. return e -> data.clearSignals(); } - long addressed = address.getUnsignedValue(); + long addressed = address.getValues().getUnsignedValueLong(); if (read.equals(rWBit.getValue())) { BitVector storedData = memory.getCell(addressed); return e -> data.feedSignals(storedData); } - else + BitVector transData = data.getValues(); + if (transData.equals(memory.getCell(addressed))) + return null; + return e -> { - BitVector transData = data.getValues(); - return e -> - { - data.clearSignals(); - memory.setCell(addressed, transData); - }; - } + data.clearSignals(); + memory.setCell(addressed, transData); + }; } @Override