X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=net.mograsim.machine%2Fsrc%2Fnet%2Fmograsim%2Fmachine%2Fstandard%2Fmemory%2FWordAddressableMemoryAdapter.java;h=a2272669e552b0c2958cc2a708933fe9fb06a1b1;hb=939f37fb65d2057c3f370214cc2eebd3e9989f69;hp=ffacb74e3965d940ac4587d803ddf5fbe84dbedb;hpb=9aeb97636520d2226d3d9919ddf38c0e6d0171b7;p=Mograsim.git

diff --git a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryAdapter.java b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryAdapter.java
index ffacb74e..a2272669 100644
--- a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryAdapter.java
+++ b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryAdapter.java
@@ -3,31 +3,32 @@ package net.mograsim.machine.standard.memory;
 import java.util.Map;
 
 import net.mograsim.logic.core.timeline.Timeline;
-import net.mograsim.logic.core.wires.Wire;
-import net.mograsim.logic.core.wires.Wire.ReadEnd;
-import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
+import net.mograsim.logic.core.wires.CoreWire;
+import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
+import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
 import net.mograsim.logic.model.model.wires.Pin;
-import net.mograsim.logic.model.modeladapter.LogicModelParameters;
+import net.mograsim.logic.model.modeladapter.CoreModelParameters;
 import net.mograsim.logic.model.modeladapter.componentadapters.ComponentAdapter;
 
-public class WordAddressableMemoryAdapter implements ComponentAdapter<GUIMemoryWA>
+public class WordAddressableMemoryAdapter implements ComponentAdapter<ModelMemoryWA>
 {
 
 	@Override
-	public Class<GUIMemoryWA> getSupportedClass()
+	public Class<ModelMemoryWA> getSupportedClass()
 	{
-		return GUIMemoryWA.class;
+		return ModelMemoryWA.class;
 	}
 
-	@SuppressWarnings("unused")
 	@Override
-	public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, GUIMemoryWA guiComponent,
-			Map<Pin, Wire> logicWiresPerPin)
+	public void createAndLinkComponent(Timeline timeline, CoreModelParameters params, ModelMemoryWA modelComponent,
+			Map<Pin, CoreWire> logicWiresPerPin)
 	{
-		ReadWriteEnd data = logicWiresPerPin.get(guiComponent.getDataPin()).createReadWriteEnd();
-		ReadEnd address = logicWiresPerPin.get(guiComponent.getAddressPin()).createReadOnlyEnd();
-		ReadEnd mode = logicWiresPerPin.get(guiComponent.getReadWritePin()).createReadOnlyEnd();
-		new WordAddressableMemoryComponent(timeline, 2, guiComponent.getDefinition(), data, mode, address);
+		ReadWriteEnd data = logicWiresPerPin.get(modelComponent.getDataPin()).createReadWriteEnd();
+		ReadEnd address = logicWiresPerPin.get(modelComponent.getAddressPin()).createReadOnlyEnd();
+		ReadEnd mode = logicWiresPerPin.get(modelComponent.getReadWritePin()).createReadOnlyEnd();
+		ReadEnd clock = logicWiresPerPin.get(modelComponent.getClockPin()).createReadOnlyEnd();
+		CoreWordAddressableMemory mem = new CoreWordAddressableMemory(timeline, 2, modelComponent.getDefinition(), data, mode, address, clock);
+		modelComponent.setCoreModelBinding(mem);
 	}
 
 }