X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=net.mograsim.machine%2Fsrc%2Fnet%2Fmograsim%2Fmachine%2Fstandard%2Fmemory%2FWordAddressableMemoryComponent.java;h=4cec2b17bb6af0c318c1cd195f6b3cfb1e364412;hb=153f81323a215691a0477af3fd1dd4a9d5b02958;hp=e781d3d6bad5b2dd3dbd02e210409017f6db3c6c;hpb=9aeb97636520d2226d3d9919ddf38c0e6d0171b7;p=Mograsim.git

diff --git a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java
index e781d3d6..4cec2b17 100644
--- a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java
+++ b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java
@@ -5,13 +5,12 @@ import java.util.List;
 import net.mograsim.logic.core.components.BasicComponent;
 import net.mograsim.logic.core.timeline.Timeline;
 import net.mograsim.logic.core.types.Bit;
-import net.mograsim.logic.core.types.BitVector;
 import net.mograsim.logic.core.wires.Wire.ReadEnd;
 import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
 import net.mograsim.machine.MainMemoryDefinition;
 
 /**
- * A memory component that only allows access to words of a specific length
+ * A memory component that only allows access to words of a specific width
  */
 public class WordAddressableMemoryComponent extends BasicComponent
 {
@@ -31,12 +30,12 @@ public class WordAddressableMemoryComponent extends BasicComponent
 			ReadEnd rWBit, ReadEnd address)
 	{
 		super(timeline, processTime);
-		if(data.length() != definition.getCellWidth())
-			throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.length()));
-		if(rWBit.length() != 1)
-			throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.length()));
-		if(address.length() != definition.getMemoryAddressBits())
-			throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.length()));
+		if(data.width() != definition.getCellWidth())
+			throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
+		if(rWBit.width() != 1)
+			throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
+		if(address.width() != definition.getMemoryAddressBits())
+			throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
 		this.data = data;
 		this.rWBit = rWBit;
 		this.address = address;
@@ -53,7 +52,7 @@ public class WordAddressableMemoryComponent extends BasicComponent
 		if (!address.hasNumericValue())
 		{
 			if (read.equals(rWBit.getValue()))
-				data.feedSignals(BitVector.of(Bit.U, data.length()));
+				data.feedSignals(Bit.U.toVector(data.width()));
 			else
 				data.clearSignals();
 			return;