X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=plugins%2Fnet.mograsim.logic.model.am2900%2Fcomponents%2Fnet%2Fmograsim%2Flogic%2Fmodel%2Fam2900%2Fcomponents%2F_rsLatch.json;h=8307be3bde8534baa35ee190dcbea99a59227aa7;hb=5c03a4fa605a1c3946eddece3b566b5aa0677759;hp=7a0b4b2cf9f03fba4117b2c65caa3c326a2f0c26;hpb=9e8e8ae5414f52ec87f9247b10a525f41768c7dc;p=Mograsim.git diff --git a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/_rsLatch.json b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/_rsLatch.json index 7a0b4b2c..8307be3b 100644 --- a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/_rsLatch.json +++ b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/_rsLatch.json @@ -89,7 +89,7 @@ "compName": "_submodelinterface", "pinName": "_Q" }, - "name": "_q", + "name": "unnamedWire#0", "path": [] }, { @@ -101,7 +101,7 @@ "compName": "_submodelinterface", "pinName": "Q" }, - "name": "q", + "name": "unnamedWire#1", "path": [ { "x": 35.0, @@ -130,7 +130,7 @@ "compName": "NandGate#0", "pinName": "A" }, - "name": "unnamedWire#0", + "name": "unnamedWire#2", "path": [] }, { @@ -142,7 +142,7 @@ "compName": "NandGate#1", "pinName": "B" }, - "name": "unnamedWire#1", + "name": "unnamedWire#3", "path": [ { "x": 35.0, @@ -163,7 +163,7 @@ "compName": "WireCrossPoint#0", "pinName": "" }, - "name": "unnamedWire#2", + "name": "unnamedWire#4", "path": [] }, { @@ -175,7 +175,7 @@ "compName": "WireCrossPoint#1", "pinName": "" }, - "name": "unnamedWire#3", + "name": "unnamedWire#5", "path": [ { "x": 65.0, @@ -192,7 +192,7 @@ "compName": "NandGate#1", "pinName": "A" }, - "name": "unnamedWire#4", + "name": "unnamedWire#6", "path": [] }, { @@ -204,7 +204,7 @@ "compName": "NandGate#0", "pinName": "B" }, - "name": "unnamedWire#5", + "name": "unnamedWire#7", "path": [ { "x": 65.0, @@ -240,10 +240,10 @@ "id": "wireForcing", "params": { "wiresToForce": [ - "q" + "unnamedWire#1" ], "wiresToForceInverted": [ - "_q" + "unnamedWire#0" ] } }