X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=plugins%2Fnet.mograsim.logic.model.am2900%2Fsrc%2Fnet%2Fmograsim%2Flogic%2Fmodel%2Fexamples%2FVerilogExporter.java;h=daef1aac52a577c3431e0b36ee325b49bedd607e;hb=0072642bcbf00c26d9a96796257c0caec0390e22;hp=1f9c72f02fe2c39c3e82bf780a5bfc33d4d1ca81;hpb=3e740982394864e95786d33405fe1cad2583cead;p=Mograsim.git

diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
index 1f9c72f0..daef1aac 100644
--- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
+++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
@@ -18,6 +18,7 @@ import java.util.Set;
 import java.util.stream.Collectors;
 
 import com.google.gson.JsonElement;
+import com.google.gson.JsonNull;
 
 import net.mograsim.logic.model.am2900.Am2900Loader;
 import net.mograsim.logic.model.model.LogicModelModifiable;
@@ -304,13 +305,14 @@ public class VerilogExporter
 
 	private void appendInterface(StringBuilder result)
 	{
+		result.append("input rst, input clk");
 		if (!sortedInterfacePinNames.isEmpty())
 		{
 			Map<String, Integer> logicWidthsPerInterfacePinName = Arrays.stream(componentJson.interfacePins)
 					.collect(Collectors.toMap(p -> p.name, p -> p.logicWidth));
-			result.append('\n');
 			for (int i = 0; i < sortedInterfacePinNames.size(); i++)
 			{
+				result.append(",\n");
 				String interfacePinName = sortedInterfacePinNames.get(i);
 				int logicWidth = logicWidthsPerInterfacePinName.get(interfacePinName);
 
@@ -324,10 +326,8 @@ public class VerilogExporter
 				appendLogicWidth(result, logicWidth);
 				result.append(sanitizeVerilog(interfacePinName));
 				result.append("_res");
-				if (i != sortedInterfacePinNames.size() - 1)
-					result.append(',');
-				result.append('\n');
 			}
+			result.append('\n');
 		}
 	}
 
@@ -394,7 +394,12 @@ public class VerilogExporter
 
 			result.append("assign ");
 			result.append(sanitizeVerilog(resultWireName));
-			result.append(" = ");
+			result.append(" = rst ? ");
+			result.append(logicWidth * 2);
+			result.append("'b");
+			for (int i = 0; i < logicWidth; i++)
+				result.append("10");
+			result.append(" : ");
 			result.append(sanitizeVerilog(lastWireName));
 			result.append(";\n");
 		}
@@ -420,10 +425,15 @@ public class VerilogExporter
 			}
 
 			result.append(COMPONENT_PREFIX);
-			result.append(sanitizeVerilog(subcomponentID + subcomponentParams.params));
-			result.append(" (");
+			String paramsString = subcomponentParams.params == JsonNull.INSTANCE ? "" : subcomponentParams.params.toString();
+			result.append(sanitizeVerilog(subcomponentID + paramsString));
+			result.append(' ');
+			// abuse the pinIdentifierGenerator for making these unique
+			result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
+			result.append(" (rst, clk");
 			for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
 			{
+				result.append(",\n  ");
 				String innerPinID = pinIdentifierGenerator.getPinID(subcomponentName, subcomponentInterfacePinNames.get(i));
 
 				String lastWireName;
@@ -447,8 +457,6 @@ public class VerilogExporter
 				result.append(sanitizeVerilog(nextWireName));
 				result.append(", ");
 				result.append(sanitizeVerilog(resultWireName));
-				if (i != subcomponentInterfacePinNames.size() - 1)
-					result.append(", \n  ");
 			}
 			result.append(");\n\n");
 		}