X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=plugins%2Fnet.mograsim.logic.model.am2900%2Fsrc%2Fnet%2Fmograsim%2Flogic%2Fmodel%2Fexamples%2FVerilogExporter.java;h=daef1aac52a577c3431e0b36ee325b49bedd607e;hb=0072642bcbf00c26d9a96796257c0caec0390e22;hp=e1d60bc5dd4f999cc0531ca74f205bf8e4fd2b1a;hpb=b1933553071bd1f24890a6d4d6bd91f555db69c2;p=Mograsim.git

diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
index e1d60bc5..daef1aac 100644
--- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
+++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
@@ -305,7 +305,7 @@ public class VerilogExporter
 
 	private void appendInterface(StringBuilder result)
 	{
-		result.append("input rst");
+		result.append("input rst, input clk");
 		if (!sortedInterfacePinNames.isEmpty())
 		{
 			Map<String, Integer> logicWidthsPerInterfacePinName = Arrays.stream(componentJson.interfacePins)
@@ -430,7 +430,7 @@ public class VerilogExporter
 			result.append(' ');
 			// abuse the pinIdentifierGenerator for making these unique
 			result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
-			result.append(" (rst");
+			result.append(" (rst, clk");
 			for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
 			{
 				result.append(",\n  ");