X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=plugins%2Fnet.mograsim.logic.model.am2900%2Fsrc%2Fnet%2Fmograsim%2Flogic%2Fmodel%2Fexamples%2FVerilogExporter.java;h=e1d60bc5dd4f999cc0531ca74f205bf8e4fd2b1a;hb=f19559f6899a17526e24a13127743449afb06fa2;hp=e5c244359065d168aa096c26f2111ad1dd7c389e;hpb=1ba2964fff70dc12a24084e027488d17c3924706;p=Mograsim.git

diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
index e5c24435..e1d60bc5 100644
--- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
+++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
@@ -305,13 +305,14 @@ public class VerilogExporter
 
 	private void appendInterface(StringBuilder result)
 	{
+		result.append("input rst");
 		if (!sortedInterfacePinNames.isEmpty())
 		{
 			Map<String, Integer> logicWidthsPerInterfacePinName = Arrays.stream(componentJson.interfacePins)
 					.collect(Collectors.toMap(p -> p.name, p -> p.logicWidth));
-			result.append('\n');
 			for (int i = 0; i < sortedInterfacePinNames.size(); i++)
 			{
+				result.append(",\n");
 				String interfacePinName = sortedInterfacePinNames.get(i);
 				int logicWidth = logicWidthsPerInterfacePinName.get(interfacePinName);
 
@@ -325,10 +326,8 @@ public class VerilogExporter
 				appendLogicWidth(result, logicWidth);
 				result.append(sanitizeVerilog(interfacePinName));
 				result.append("_res");
-				if (i != sortedInterfacePinNames.size() - 1)
-					result.append(',');
-				result.append('\n');
 			}
+			result.append('\n');
 		}
 	}
 
@@ -395,7 +394,12 @@ public class VerilogExporter
 
 			result.append("assign ");
 			result.append(sanitizeVerilog(resultWireName));
-			result.append(" = ");
+			result.append(" = rst ? ");
+			result.append(logicWidth * 2);
+			result.append("'b");
+			for (int i = 0; i < logicWidth; i++)
+				result.append("10");
+			result.append(" : ");
 			result.append(sanitizeVerilog(lastWireName));
 			result.append(";\n");
 		}
@@ -423,9 +427,13 @@ public class VerilogExporter
 			result.append(COMPONENT_PREFIX);
 			String paramsString = subcomponentParams.params == JsonNull.INSTANCE ? "" : subcomponentParams.params.toString();
 			result.append(sanitizeVerilog(subcomponentID + paramsString));
-			result.append(" (");
+			result.append(' ');
+			// abuse the pinIdentifierGenerator for making these unique
+			result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
+			result.append(" (rst");
 			for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
 			{
+				result.append(",\n  ");
 				String innerPinID = pinIdentifierGenerator.getPinID(subcomponentName, subcomponentInterfacePinNames.get(i));
 
 				String lastWireName;
@@ -449,8 +457,6 @@ public class VerilogExporter
 				result.append(sanitizeVerilog(nextWireName));
 				result.append(", ");
 				result.append(sanitizeVerilog(resultWireName));
-				if (i != subcomponentInterfacePinNames.size() - 1)
-					result.append(", \n  ");
 			}
 			result.append(");\n\n");
 		}