X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=plugins%2Fnet.mograsim.logic.model.am2900%2Fsrc%2Fnet%2Fmograsim%2Flogic%2Fmodel%2Fexamples%2FVerilogExporter.java;h=fb1fd2f402c14058254d3c78a0a5e35c0ad044e6;hb=590c4809a069b0d30529735bf58f0db5382f8a88;hp=70907f14454f9c1135b5591c4c32b3fc2c8f8ef0;hpb=dfeebad528797afaf1889ba0bd81a248fba00420;p=Mograsim.git

diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
index 70907f14..fb1fd2f4 100644
--- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
+++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
@@ -229,7 +229,8 @@ public class VerilogExporter
 	{
 		return combinedInterfacePinsPerComponentID.entrySet().stream().collect(Collectors.toMap(Entry::getKey, e ->
 		{
-			List<String> names = e.getValue().values().stream().distinct().collect(Collectors.toList());
+			List<String> names = e.getValue().values().stream().distinct().sorted().collect(Collectors.toList());
+			System.out.println("Assuming following order for interface pins of " + e.getKey() + ": " + names);
 			Map<String, Integer> widthesPerName = Arrays.stream(componentsById.get(e.getKey()).interfacePins)
 					.collect(Collectors.toMap(p -> p.name, p -> p.logicWidth));
 			List<Integer> widthes = names.stream().map(widthesPerName::get).collect(Collectors.toList());
@@ -305,13 +306,14 @@ public class VerilogExporter
 
 	private void appendInterface(StringBuilder result)
 	{
+		result.append("input rst, input clk");
 		if (!sortedInterfacePinNames.isEmpty())
 		{
 			Map<String, Integer> logicWidthsPerInterfacePinName = Arrays.stream(componentJson.interfacePins)
 					.collect(Collectors.toMap(p -> p.name, p -> p.logicWidth));
-			result.append('\n');
 			for (int i = 0; i < sortedInterfacePinNames.size(); i++)
 			{
+				result.append(",\n");
 				String interfacePinName = sortedInterfacePinNames.get(i);
 				int logicWidth = logicWidthsPerInterfacePinName.get(interfacePinName);
 
@@ -325,10 +327,8 @@ public class VerilogExporter
 				appendLogicWidth(result, logicWidth);
 				result.append(sanitizeVerilog(interfacePinName));
 				result.append("_res");
-				if (i != sortedInterfacePinNames.size() - 1)
-					result.append(',');
-				result.append('\n');
 			}
+			result.append('\n');
 		}
 	}
 
@@ -395,7 +395,12 @@ public class VerilogExporter
 
 			result.append("assign ");
 			result.append(sanitizeVerilog(resultWireName));
-			result.append(" = ");
+			result.append(" = rst ? ");
+			result.append(logicWidth * 2);
+			result.append("'b");
+			for (int i = 0; i < logicWidth; i++)
+				result.append("10");
+			result.append(" : ");
 			result.append(sanitizeVerilog(lastWireName));
 			result.append(";\n");
 		}
@@ -426,9 +431,10 @@ public class VerilogExporter
 			result.append(' ');
 			// abuse the pinIdentifierGenerator for making these unique
 			result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
-			result.append(" (");
+			result.append(" (rst, clk");
 			for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
 			{
+				result.append(",\n  ");
 				String innerPinID = pinIdentifierGenerator.getPinID(subcomponentName, subcomponentInterfacePinNames.get(i));
 
 				String lastWireName;
@@ -452,13 +458,13 @@ public class VerilogExporter
 				result.append(sanitizeVerilog(nextWireName));
 				result.append(", ");
 				result.append(sanitizeVerilog(resultWireName));
-				if (i != subcomponentInterfacePinNames.size() - 1)
-					result.append(", \n  ");
 			}
 			result.append(");\n\n");
 		}
 	}
 
+	private static Map<Tuple2<String, JsonElement>, Tuple2<List<String>, List<Integer>>> atomicComponentInterfaces = new HashMap<>();
+
 	private Tuple2<List<String>, List<Integer>> getSubcomponentInterfacePinNamesAndWidths(String subcomponentID,
 			JsonElement subcomponentParams)
 	{
@@ -466,13 +472,23 @@ public class VerilogExporter
 		if (result != null)
 			return result;
 
+		Tuple2<String, JsonElement> subcomponentKey = new Tuple2<>(subcomponentID, subcomponentParams);
+
+		result = atomicComponentInterfaces.get(subcomponentKey);
+		if (result != null)
+			return result;
+
 		Map<String, Pin> pins = IndirectModelComponentCreator
 				.createComponent(new LogicModelModifiable(), subcomponentID, subcomponentParams).getPins();
 		List<String> names = pins.keySet().stream().sorted().collect(Collectors.toList());
 		List<Integer> widthes = pins.entrySet().stream().sorted(Comparator.comparing(e -> e.getKey())).map(Entry::getValue)
 				.map(p -> p.logicWidth).collect(Collectors.toList());
-		System.out.println("Assuming following order for interface pins of " + subcomponentID + ": " + names);
-		return new Tuple2<>(names, widthes);
+		System.out.println(
+				"Assuming following order for interface pins of " + subcomponentID + " with params " + subcomponentParams + ": " + names);
+		result = new Tuple2<>(names, widthes);
+
+		atomicComponentInterfaces.put(subcomponentKey, result);
+		return result;
 	}
 
 	private static void appendLogicWidth(StringBuilder result, int logicWidth)
@@ -537,6 +553,41 @@ public class VerilogExporter
 			this.e1 = e1;
 			this.e2 = e2;
 		}
+
+		@Override
+		public int hashCode()
+		{
+			final int prime = 31;
+			int result = 1;
+			result = prime * result + ((e1 == null) ? 0 : e1.hashCode());
+			result = prime * result + ((e2 == null) ? 0 : e2.hashCode());
+			return result;
+		}
+
+		@Override
+		public boolean equals(Object obj)
+		{
+			if (this == obj)
+				return true;
+			if (obj == null)
+				return false;
+			if (getClass() != obj.getClass())
+				return false;
+			Tuple2<?, ?> other = (Tuple2<?, ?>) obj;
+			if (e1 == null)
+			{
+				if (other.e1 != null)
+					return false;
+			} else if (!e1.equals(other.e1))
+				return false;
+			if (e2 == null)
+			{
+				if (other.e2 != null)
+					return false;
+			} else if (!e2.equals(other.e2))
+				return false;
+			return true;
+		}
 	}
 
 	private static String sanitizeVerilog(String str)