X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=plugins%2Fnet.mograsim.logic.model.am2900%2Fsrc%2Fnet%2Fmograsim%2Flogic%2Fmodel%2Fexamples%2FVerilogExporter.java;h=fb1fd2f402c14058254d3c78a0a5e35c0ad044e6;hb=83a0505e2c104f18ffc6c67c25f523c72cac88a5;hp=e1d60bc5dd4f999cc0531ca74f205bf8e4fd2b1a;hpb=f19559f6899a17526e24a13127743449afb06fa2;p=Mograsim.git diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java index e1d60bc5..fb1fd2f4 100644 --- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java +++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java @@ -229,7 +229,8 @@ public class VerilogExporter { return combinedInterfacePinsPerComponentID.entrySet().stream().collect(Collectors.toMap(Entry::getKey, e -> { - List names = e.getValue().values().stream().distinct().collect(Collectors.toList()); + List names = e.getValue().values().stream().distinct().sorted().collect(Collectors.toList()); + System.out.println("Assuming following order for interface pins of " + e.getKey() + ": " + names); Map widthesPerName = Arrays.stream(componentsById.get(e.getKey()).interfacePins) .collect(Collectors.toMap(p -> p.name, p -> p.logicWidth)); List widthes = names.stream().map(widthesPerName::get).collect(Collectors.toList()); @@ -305,7 +306,7 @@ public class VerilogExporter private void appendInterface(StringBuilder result) { - result.append("input rst"); + result.append("input rst, input clk"); if (!sortedInterfacePinNames.isEmpty()) { Map logicWidthsPerInterfacePinName = Arrays.stream(componentJson.interfacePins) @@ -430,7 +431,7 @@ public class VerilogExporter result.append(' '); // abuse the pinIdentifierGenerator for making these unique result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName)); - result.append(" (rst"); + result.append(" (rst, clk"); for (int i = 0; i < subcomponentInterfacePinNames.size(); i++) { result.append(",\n "); @@ -462,6 +463,8 @@ public class VerilogExporter } } + private static Map, Tuple2, List>> atomicComponentInterfaces = new HashMap<>(); + private Tuple2, List> getSubcomponentInterfacePinNamesAndWidths(String subcomponentID, JsonElement subcomponentParams) { @@ -469,13 +472,23 @@ public class VerilogExporter if (result != null) return result; + Tuple2 subcomponentKey = new Tuple2<>(subcomponentID, subcomponentParams); + + result = atomicComponentInterfaces.get(subcomponentKey); + if (result != null) + return result; + Map pins = IndirectModelComponentCreator .createComponent(new LogicModelModifiable(), subcomponentID, subcomponentParams).getPins(); List names = pins.keySet().stream().sorted().collect(Collectors.toList()); List widthes = pins.entrySet().stream().sorted(Comparator.comparing(e -> e.getKey())).map(Entry::getValue) .map(p -> p.logicWidth).collect(Collectors.toList()); - System.out.println("Assuming following order for interface pins of " + subcomponentID + ": " + names); - return new Tuple2<>(names, widthes); + System.out.println( + "Assuming following order for interface pins of " + subcomponentID + " with params " + subcomponentParams + ": " + names); + result = new Tuple2<>(names, widthes); + + atomicComponentInterfaces.put(subcomponentKey, result); + return result; } private static void appendLogicWidth(StringBuilder result, int logicWidth) @@ -540,6 +553,41 @@ public class VerilogExporter this.e1 = e1; this.e2 = e2; } + + @Override + public int hashCode() + { + final int prime = 31; + int result = 1; + result = prime * result + ((e1 == null) ? 0 : e1.hashCode()); + result = prime * result + ((e2 == null) ? 0 : e2.hashCode()); + return result; + } + + @Override + public boolean equals(Object obj) + { + if (this == obj) + return true; + if (obj == null) + return false; + if (getClass() != obj.getClass()) + return false; + Tuple2 other = (Tuple2) obj; + if (e1 == null) + { + if (other.e1 != null) + return false; + } else if (!e1.equals(other.e1)) + return false; + if (e2 == null) + { + if (other.e2 != null) + return false; + } else if (!e2.equals(other.e2)) + return false; + return true; + } } private static String sanitizeVerilog(String str)