X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=plugins%2Fnet.mograsim.logic.model.verilog%2Fsrc%2Fnet%2Fmograsim%2Flogic%2Fmodel%2Fverilog%2Fconverter%2FModelComponentToVerilogComponentDeclarationMapping.java;h=b05e152b5649934c889af580ca92e3026144e50b;hb=c6087221c312e76ad07cf75da61c735278ab8634;hp=808ac51fb4416b3c24668f54e48bed0ba9ff6d7e;hpb=2e8be4681cb856e99697df230fa453b30794e201;p=Mograsim.git

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogComponentDeclarationMapping.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogComponentDeclarationMapping.java
index 808ac51f..b05e152b 100644
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogComponentDeclarationMapping.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogComponentDeclarationMapping.java
@@ -7,6 +7,7 @@ import java.util.List;
 import java.util.Map;
 import java.util.Objects;
 import java.util.Set;
+import java.util.stream.Collectors;
 
 import com.google.gson.JsonElement;
 
@@ -20,6 +21,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping
 	private final VerilogComponentDeclaration verilogComponentDeclaration;
 	private final Set<VerilogEmulatedModelPin> pinMapping;
 
+	private final Set<Set<PinNameBit>> internallyConnectedPins;
 	private final Map<PinNameBit, VerilogEmulatedModelPin> prePinMapping;
 	private final Map<PinNameBit, VerilogEmulatedModelPin> outPinMapping;
 	private final Map<PinNameBit, VerilogEmulatedModelPin> resPinMapping;
@@ -35,6 +37,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping
 
 		this.reversePinMapping = checkAndCalculateReversePinMapping();
 
+		this.internallyConnectedPins = calculateInternallyConnectedPins();
 		this.prePinMapping = filterPinMapping(Type.PRE);
 		this.outPinMapping = filterPinMapping(Type.OUT);
 		this.resPinMapping = filterPinMapping(Type.RES);
@@ -67,6 +70,11 @@ public class ModelComponentToVerilogComponentDeclarationMapping
 		return reverseMapping;
 	}
 
+	private Set<Set<PinNameBit>> calculateInternallyConnectedPins()
+	{
+		return pinMapping.stream().map(VerilogEmulatedModelPin::getPinbits).collect(Collectors.toUnmodifiableSet());
+	}
+
 	private Map<PinNameBit, VerilogEmulatedModelPin> filterPinMapping(Type filteredType)
 	{
 		Map<PinNameBit, VerilogEmulatedModelPin> result = new HashMap<>();
@@ -92,6 +100,11 @@ public class ModelComponentToVerilogComponentDeclarationMapping
 		return verilogComponentDeclaration;
 	}
 
+	public Set<Set<PinNameBit>> getInternallyConnectedPins()
+	{
+		return internallyConnectedPins;
+	}
+
 	public Set<VerilogEmulatedModelPin> getPinMapping()
 	{
 		return pinMapping;
@@ -123,6 +136,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping
 		final int prime = 31;
 		int result = 1;
 		result = prime * result + ((modelComponentID == null) ? 0 : modelComponentID.hashCode());
+		result = prime * result + ((modelComponentParams == null) ? 0 : modelComponentParams.hashCode());
 		result = prime * result + ((pinMapping == null) ? 0 : pinMapping.hashCode());
 		result = prime * result + ((verilogComponentDeclaration == null) ? 0 : verilogComponentDeclaration.hashCode());
 		return result;
@@ -144,6 +158,12 @@ public class ModelComponentToVerilogComponentDeclarationMapping
 				return false;
 		} else if (!modelComponentID.equals(other.modelComponentID))
 			return false;
+		if (modelComponentParams == null)
+		{
+			if (other.modelComponentParams != null)
+				return false;
+		} else if (!modelComponentParams.equals(other.modelComponentParams))
+			return false;
 		if (pinMapping == null)
 		{
 			if (other.pinMapping != null)