X-Git-Url: https://mograsim.net/gitweb/?a=blobdiff_plain;f=plugins%2Fnet.mograsim.machine%2Fsrc%2Fnet%2Fmograsim%2Fmachine%2Fstandard%2Fmemory%2FCoreWordAddressableMemory.java;h=801895be2b903d3f50579d2831c5093047b38306;hb=f098cd47d06be0cc654532a5fad0e5e89f0ef93c;hp=40abba9f92e3501d20005c8e29f9d6c199579153;hpb=58babf45ae7d259a296656451d796dbe601377a4;p=Mograsim.git

diff --git a/plugins/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java b/plugins/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
index 40abba9f..801895be 100644
--- a/plugins/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
+++ b/plugins/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
@@ -11,17 +11,20 @@ import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
 import net.mograsim.machine.MainMemory;
 import net.mograsim.machine.MainMemoryDefinition;
+import net.mograsim.machine.Memory.MemoryCellModifiedListener;
 
 /**
  * A memory component that only allows access to words of a specific width
  */
 public class CoreWordAddressableMemory extends BasicCoreComponent
 {
-	private final MainMemory memory;
 	private final static Bit read = Bit.ONE;
 
 	private ReadWriteEnd data;
 	private ReadEnd rWBit, address;
+	private final MemoryCellModifiedListener memObs;
+	private final MainMemoryDefinition definition;
+	private MainMemory memory;
 
 	/**
 	 * @param data    The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
@@ -29,11 +32,10 @@ public class CoreWordAddressableMemory extends BasicCoreComponent
 	 * @param rWBit   The value of the 0th bit dictates the mode: 0: Write, 1: Read
 	 * @param address The bits of this ReadEnd address the memory cell to read/write
 	 */
-	public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data, ReadEnd rWBit,
+	public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data, ReadEnd rWBit,
 			ReadEnd address)
 	{
 		super(timeline, processTime);
-		MainMemoryDefinition definition = memory.getDefinition();
 		if (data.width() != definition.getCellWidth())
 			throw new IllegalArgumentException(
 					String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d",
@@ -45,19 +47,38 @@ public class CoreWordAddressableMemory extends BasicCoreComponent
 			throw new IllegalArgumentException(
 					String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d",
 							definition.getMemoryAddressBits(), address.width()));
-		this.memory = memory;
 		this.data = data;
 		this.rWBit = rWBit;
 		this.address = address;
-		memory.registerObserver(a -> update());
+		this.definition = definition;
+		this.memObs = a -> update();
 		data.registerObserver(this);
 		rWBit.registerObserver(this);
 		address.registerObserver(this);
 	}
 
+	public void setMemory(MainMemory memory)
+	{
+		if (memory != null && !memory.getDefinition().equals(definition))
+			throw new IllegalArgumentException("Memory of incorrect memory definition given");
+		if (this.memory != null)
+			this.memory.registerCellModifiedListener(memObs);
+		this.memory = memory;
+		if (memory != null)
+			memory.registerCellModifiedListener(memObs);
+		update();
+	}
+
+	public MainMemory getMemory()
+	{
+		return memory;
+	}
+
 	@Override
 	protected TimelineEventHandler compute()
 	{
+		if (memory == null)
+			return e -> data.feedSignals(Bit.U.toVector(data.width()));
 		if (!address.getValues().isBinary())
 		{
 			if (read.equals(rWBit.getValue()))