VerilogExporter now "hands through" a clk signal
authorDaniel Kirschten <daniel.kirschten@gmx.de>
Sun, 1 Mar 2020 16:26:28 +0000 (17:26 +0100)
committerDaniel Kirschten <daniel.kirschten@gmx.de>
Wed, 25 Mar 2020 13:08:26 +0000 (14:08 +0100)
commit0072642bcbf00c26d9a96796257c0caec0390e22
tree1c136e16061522e1f2bb38c8354ac575e1cb490e
parentf19559f6899a17526e24a13127743449afb06fa2
VerilogExporter now "hands through" a clk signal

to avoid combinatorial loops
plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java