Made Am2900 memory reads work if Am2901Dest=QREG ...

Made Am2900 memory reads work if Am2901Dest=QREG ...

at the expense of U forming shortly in the D bus when the second cycle
of a read starts, if the D bus is used in the first cycle; due to the
memory controller's TriStateBuffers being en- and disabled earlier than
the other TriStateBuffers writing to the buses.
U also forms in the D bus when the cycle after the second one of a read
starts, but this is due to the RAM chip shortly outputting U due to the
address changing to X, because the A bus holds Z in the second cycle of
a read.
Writes don't have these kind of problems since the memory controller
obviously doesn't output anything on the D bus when writing.