Added gate/wire delay in SubmodelComponentTestbench
authorDaniel Kirschten <daniel.kirschten@gmx.de>
Tue, 4 Jun 2019 13:32:13 +0000 (15:32 +0200)
committerDaniel Kirschten <daniel.kirschten@gmx.de>
Tue, 4 Jun 2019 13:32:13 +0000 (15:32 +0200)
commitc6eb49c9565b3086b14071399d915e070d939c47
treeae534f998b5e16322bd938ca6dacd630dfde7f45
parent5d4cf0e5ccbbbd967f89f605e24ba61ceacc15dc
Added gate/wire delay in SubmodelComponentTestbench
net.mograsim.logic.ui/src/net/mograsim/logic/ui/examples/SubmodelComponentTestbench.java