\r
import era.mi.logic.Bit;\r
import era.mi.logic.Simulation;\r
+import era.mi.logic.components.Connector;\r
import era.mi.logic.components.Demux;\r
import era.mi.logic.components.Merger;\r
import era.mi.logic.components.Mux;\r
import era.mi.logic.wires.WireArray;\r
import era.mi.logic.wires.WireArray.WireArrayEnd;\r
\r
+@SuppressWarnings("unused")\r
class ComponentTest\r
{\r
\r
WireArrayEnd enI = en.createInput(), aI = a.createInput(), bI = b.createInput();\r
enI.feedSignals(Bit.ONE);\r
aI.feedSignals(Bit.ONE);\r
+ bI.feedSignals(Bit.Z);\r
\r
Simulation.TIMELINE.executeAll();\r
\r
assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);\r
}\r
\r
-// @Test\r
+ @Test\r
void wireConnections()\r
{\r
// Nur ein Experiment, was über mehrere 'passive' Bausteine hinweg passieren würde\r
cI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
\r
- new Connector(b, c);\r
+ new Connector(b, c).connect();\r
test.assertAfterSimulationIs(print, Bit.Z);\r
System.err.println("ONE");\r
bI.feedSignals(Bit.ONE);\r
bI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
\r
- new Connector(a, b);\r
+ new Connector(a, b).connect();\r
System.err.println("Z 2");\r
aI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
Bit[] bits = input.getValues();\r
for (int i = 0; i < length; i++)\r
{\r
- if (Bit.Z.equals(bits[i]) || newValues[i].equals(bits[i]))\r
- continue;\r
- else if (Bit.Z.equals(newValues[i]))\r
- newValues[i] = bits[i];\r
- else\r
- newValues[i] = Bit.X;\r
+ newValues[i] = newValues[i].combineWith(bits[i]);\r
}\r
}\r
\r