import net.mograsim.logic.core.types.BitVector;\r
import net.mograsim.logic.core.wires.Wire;\r
import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;\r
+import net.mograsim.machine.DefaultMainMemoryDefinition;\r
\r
class WordAddressableMemoryTest {\r
\r
ReadWriteEnd dataI = data.createReadWriteEnd();\r
ReadWriteEnd addressI = address.createReadWriteEnd();\r
\r
- WordAddressableMemoryComponent memory = new WordAddressableMemoryComponent(t, 4, 4096L, Long.MAX_VALUE, data.createReadWriteEnd(),\r
+ WordAddressableMemoryComponent memory = new WordAddressableMemoryComponent(t, 4, new DefaultMainMemoryDefinition(64, 16, 4096L, Long.MAX_VALUE), data.createReadWriteEnd(),\r
rW.createReadOnlyEnd(), address.createReadOnlyEnd());\r
\r
Random r = new Random();\r