--- /dev/null
+package net.mograsim.logic.core.components.gates;
+
+import java.util.Arrays;
+import java.util.HashMap;
+import java.util.List;
+
+import net.mograsim.logic.core.components.BasicComponent;
+import net.mograsim.logic.core.timeline.Timeline;
+import net.mograsim.logic.core.types.Bit;
+import net.mograsim.logic.core.types.BitVector;
+import net.mograsim.logic.core.wires.Wire.ReadEnd;
+import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
+
+public class WordAddressableMemoryComponent extends BasicComponent
+{
+ private final WordAddressableMemory memory;
+ private final static Bit read = Bit.ONE;
+
+ private ReadWriteEnd data;
+ private ReadEnd rWBit, address;
+
+ /**
+ *
+ * @param timeline
+ * @param processTime
+ * @param minimalAddress
+ * @param maximalAddress
+ * @param data
+ * @param rWBit 0: Write 1: Read
+ * @param address
+ */
+ public WordAddressableMemoryComponent(Timeline timeline, int processTime, long minimalAddress, long maximalAddress, ReadWriteEnd data,
+ ReadEnd rWBit, ReadEnd address)
+ {
+ super(timeline, processTime);
+ this.data = data;
+ this.rWBit = rWBit;
+ this.address = address;
+ data.registerObserver(this);
+ rWBit.registerObserver(this);
+ address.registerObserver(this);
+
+ memory = new WordAddressableMemory(data.length(), minimalAddress, maximalAddress);
+ }
+
+ @Override
+ protected void compute()
+ {
+ if (!address.hasNumericValue())
+ {
+ if (read.equals(rWBit.getValue()))
+ data.feedSignals(BitVector.of(Bit.U, data.length()));
+ else
+ data.clearSignals();
+ return;
+ }
+ long addressed = address.getUnsignedValue();
+ if (read.equals(rWBit.getValue()))
+ data.feedSignals(memory.getCell(addressed));
+ else
+ {
+ data.clearSignals();
+ System.out.println(memory);
+ memory.setCell(addressed, data.getValues());
+ }
+ }
+
+ @Override
+ public List<ReadEnd> getAllInputs()
+ {
+ return List.of(data, rWBit, address);
+ }
+
+ @Override
+ public List<ReadWriteEnd> getAllOutputs()
+ {
+ return List.of(data);
+ }
+
+ private class WordAddressableMemory
+ {
+ private final int cellWidth;
+ private final long minimalAddress, maximalAddress;
+ private final int pageSize;
+
+ private HashMap<Long, Page> pages;
+
+ public WordAddressableMemory(int cellWidth, long minimalAddress, long maximalAddress)
+ {
+ super();
+ this.cellWidth = cellWidth;
+ this.minimalAddress = minimalAddress;
+ this.maximalAddress = maximalAddress;
+ this.pages = new HashMap<>();
+ this.pageSize = 64;
+ }
+
+ public void setCell(long address, BitVector b)
+ {
+ if (address < minimalAddress || address > maximalAddress)
+ throw new IndexOutOfBoundsException(String.format("Memory address out of bounds! Minimum: %d Maimum: %d Actual: %d",
+ minimalAddress, maximalAddress, address));
+ long page = address / pageSize;
+ int offset = (int) (address % pageSize);
+ Page p = pages.get(Long.valueOf(page));
+ if (p == null)
+ pages.put(page, p = new Page());
+ p.setCell(offset, b);
+ }
+
+ public BitVector getCell(long address)
+ {
+ long page = address / pageSize;
+ int offset = (int) (address % pageSize);
+ Page p = pages.get(Long.valueOf(page));
+ if (p == null)
+ return BitVector.of(Bit.U, cellWidth);
+ return p.getCell(offset);
+ }
+
+ private class Page
+ {
+ private BitVector[] memory;
+
+ public Page()
+ {
+ memory = new BitVector[pageSize];
+ }
+
+ public BitVector getCell(int index)
+ {
+ BitVector b = memory[index];
+ if (b == null)
+ return BitVector.of(Bit.U, cellWidth);
+ return memory[index];
+ }
+
+ public void setCell(int index, BitVector bits)
+ {
+ if (bits.length() != cellWidth)
+ throw new IllegalArgumentException(
+ String.format("BitVector to be saved in memory cell has unexpected length. Expected: %d Actual: %d", cellWidth,
+ bits.length()));
+ memory[index] = bits;
+ }
+
+ @Override
+ public String toString()
+ {
+ return Arrays.deepToString(memory);
+ }
+ }
+ }
+}
+//import java.math.BigInteger;
+//
+//import net.mograsim.logic.core.types.Bit;
+//import net.mograsim.logic.core.types.BitVector;
+//
+//private byte[] encode(BitVector v)
+//{
+// BigInteger d = BigInteger.ZERO;
+// Bit[] bits = v.getBits();
+// for (int i = v.length() - 1; i >= 0; i--)
+// {
+// d = d.add(BigInteger.valueOf(bits[i].ordinal()));
+// d = d.multiply(BigInteger.valueOf(Bit.values().length));
+// }
+// return d.toByteArray();
+//}
+//
+///**
+// *
+// * @param bytes
+// * @param numBits length of the resulting BitVector
+// * @return
+// */
+//private BitVector decode(byte[] bytes, int numBits)
+//{
+// BigInteger d = new BigInteger(bytes);
+// Bit[] bits = new Bit[numBits];
+// return BitVector.of(bits);
+//}
+//
+//private static class CellArray
+//{
+// private byte[] bytes;
+// private final static byte mask = -1;
+// public CellArray(int numCells, int cellSize)
+// {
+// bytes = new byte[numCells * cellSize / 8];
+// }
+//
+// public byte[] getCell(int i)
+// {
+//
+// }
+//}
import static org.junit.jupiter.api.Assertions.assertEquals;\r
import static org.junit.jupiter.api.Assertions.fail;\r
\r
+import java.math.BigInteger;\r
+import java.util.Random;\r
import java.util.function.LongConsumer;\r
\r
+import org.junit.Before;\r
import org.junit.jupiter.api.Test;\r
\r
import net.mograsim.logic.core.components.Connector;\r
import net.mograsim.logic.core.components.gates.NorGate;\r
import net.mograsim.logic.core.components.gates.NotGate;\r
import net.mograsim.logic.core.components.gates.OrGate;\r
+import net.mograsim.logic.core.components.gates.WordAddressableMemoryComponent;\r
import net.mograsim.logic.core.components.gates.XorGate;\r
import net.mograsim.logic.core.timeline.Timeline;\r
import net.mograsim.logic.core.types.Bit;\r
{\r
private Timeline t = new Timeline(11);\r
\r
+ @Before\r
+ void resetTimeline()\r
+ {\r
+ t.reset();\r
+ }\r
+\r
@Test\r
void circuitExampleTest()\r
{\r
@Test\r
void splitterTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), in = new Wire(t, 8, 1);\r
in.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
new Splitter(t, in.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(), c.createReadWriteEnd());\r
@Test\r
void mergerTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), out = new Wire(t, 8, 1);\r
a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO);\r
b.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO);\r
@Test\r
void fusionTest1()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), out = new Wire(t, 8, 1);\r
Wire.fuse(a, out, 0, 0, a.length);\r
Wire.fuse(b, out, 0, a.length, b.length);\r
@Test\r
void fusionTest2()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 1);\r
Wire.fuse(a, b);\r
ReadWriteEnd rw = a.createReadWriteEnd();\r
@Test\r
void fusionTest3()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 1);\r
a.createReadWriteEnd().feedSignals(Bit.Z, Bit.U, Bit.X);\r
t.executeAll();\r
@Test\r
void muxTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 4, 3), b = new Wire(t, 4, 6), c = new Wire(t, 4, 4), select = new Wire(t, 2, 5), out = new Wire(t, 4, 1);\r
ReadWriteEnd selectIn = select.createReadWriteEnd();\r
\r
@Test\r
void demuxTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 4, 3), b = new Wire(t, 4, 6), c = new Wire(t, 4, 4), select = new Wire(t, 2, 5), in = new Wire(t, 4, 1);\r
ReadWriteEnd selectIn = select.createReadWriteEnd();\r
\r
@Test\r
void andTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1);\r
new AndGate(t, 1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
@Test\r
void orTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1);\r
new OrGate(t, 1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
@Test\r
void nandTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1), d = new Wire(t, 4, 1);\r
new NandGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
@Test\r
void norTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1), d = new Wire(t, 4, 1);\r
new NorGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
@Test\r
void xorTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 2), c = new Wire(t, 3, 1), d = new Wire(t, 3, 1);\r
new XorGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
@Test\r
void notTest()\r
{\r
- t.reset();\r
Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 2);\r
new NotGate(t, 1, a.createReadOnlyEnd(), b.createReadWriteEnd());\r
a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
@Test\r
void rsLatchCircuitTest()\r
{\r
- t.reset();\r
Wire r = new Wire(t, 1, 1), s = new Wire(t, 1, 1), t1 = new Wire(t, 1, 15), t2 = new Wire(t, 1, 1), q = new Wire(t, 1, 1),\r
nq = new Wire(t, 1, 1);\r
\r
@Test\r
void numericValueTest()\r
{\r
- t.reset();\r
-\r
Wire a = new Wire(t, 4, 1);\r
a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ONE, Bit.ONE);\r
\r
@Test\r
void multipleInputs()\r
{\r
- t.reset();\r
Wire w = new Wire(t, 2, 1);\r
ReadWriteEnd wI1 = w.createReadWriteEnd(), wI2 = w.createReadWriteEnd();\r
wI1.feedSignals(Bit.ONE, Bit.Z);\r
{\r
// Nur ein Experiment, was über mehrere 'passive' Bausteine hinweg passieren würde\r
\r
- t.reset();\r
-\r
Wire a = new Wire(t, 1, 2);\r
Wire b = new Wire(t, 1, 2);\r
Wire c = new Wire(t, 1, 2);\r
test2.assertAfterSimulationIs(Bit.ONE);\r
}\r
\r
+ @Test\r
+ public void wordAddressableMemoryLargeTest()\r
+ {\r
+ Wire rW = new Wire(t, 1, 2);\r
+ Wire data = new Wire(t, 16, 2);\r
+ Wire address = new Wire(t, 64, 2);\r
+ ReadWriteEnd rWI = rW.createReadWriteEnd();\r
+ ReadWriteEnd dataI = data.createReadWriteEnd();\r
+ ReadWriteEnd addressI = address.createReadWriteEnd();\r
+\r
+ WordAddressableMemoryComponent memory = new WordAddressableMemoryComponent(t, 4, 4096L, Long.MAX_VALUE, data.createReadWriteEnd(),\r
+ rW.createReadOnlyEnd(), address.createReadOnlyEnd());\r
+\r
+ Random r = new Random();\r
+ for (long j = 1; j > 0; j *= 2)\r
+ {\r
+ for (int i = 0; i < 50; i++)\r
+ {\r
+ String sAddress = String.format("%64s", BigInteger.valueOf(4096 + i + j).toString(2)).replace(' ', '0');\r
+ sAddress = new StringBuilder(sAddress).reverse().toString();\r
+ BitVector bAddress = BitVector.parse(sAddress);\r
+ addressI.feedSignals(bAddress);\r
+ t.executeAll();\r
+ String random = BigInteger.valueOf(Math.abs(r.nextInt())).toString(5);\r
+ random = random.substring(Integer.max(0, random.length() - 16));\r
+ random = String.format("%16s", random).replace(' ', '0');\r
+ random = random.replace('2', 'X').replace('3', 'Z').replace('4', 'U');\r
+ BitVector vector = BitVector.parse(random);\r
+ dataI.feedSignals(vector);\r
+ rWI.feedSignals(Bit.ZERO);\r
+ t.executeAll();\r
+ rWI.feedSignals(Bit.ONE);\r
+ t.executeAll();\r
+ dataI.clearSignals();\r
+ t.executeAll();\r
+\r
+ assertBitArrayEquals(dataI.getValues(), vector.getBits());\r
+ }\r
+ }\r
+ }\r
+\r
private static void assertBitArrayEquals(BitVector actual, Bit... expected)\r
{\r
assertArrayEquals(expected, actual.getBits());\r
projects / Mograsim.git / commitdiff