Completion of ReadEnd and ReadWriteEnd addition

diff --git a/era.mi/src/era/mi/logic/tests/ComponentTest.java b/era.mi/src/era/mi/logic/tests/ComponentTest.java
index 805d2e5..54f47d9 100644 (file)
--- a/era.mi/src/era/mi/logic/tests/ComponentTest.java
+++ b/era.mi/src/era/mi/logic/tests/ComponentTest.java
@@ -34,17 +34,17 @@ class ComponentTest
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1), e = new Wire(1, 1), f = new Wire(1, 1),\r
                                g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1), j = new Wire(1, 1), k = new Wire(1, 1);\r
-               new AndGate(1, f.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
-               new NotGate(1, f.createReadOnlyEnd(), g.createEnd());\r
-               new Merger(h.createEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd());\r
-               new Mux(1, i.createEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd());\r
-               new Splitter(i.createReadOnlyEnd(), k.createEnd(), j.createEnd());\r
-\r
-               a.createEnd().feedSignals(Bit.ZERO);\r
-               b.createEnd().feedSignals(Bit.ONE);\r
-               c.createEnd().feedSignals(Bit.ZERO);\r
-               d.createEnd().feedSignals(Bit.ONE, Bit.ONE);\r
-               e.createEnd().feedSignals(Bit.ZERO);\r
+               new AndGate(1, f.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
+               new NotGate(1, f.createReadOnlyEnd(), g.createReadWriteEnd());\r
+               new Merger(h.createReadWriteEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd());\r
+               new Mux(1, i.createReadWriteEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd());\r
+               new Splitter(i.createReadOnlyEnd(), k.createReadWriteEnd(), j.createReadWriteEnd());\r
+\r
+               a.createReadWriteEnd().feedSignals(Bit.ZERO);\r
+               b.createReadWriteEnd().feedSignals(Bit.ONE);\r
+               c.createReadWriteEnd().feedSignals(Bit.ZERO);\r
+               d.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE);\r
+               e.createReadWriteEnd().feedSignals(Bit.ZERO);\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -57,8 +57,8 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(2, 1), c = new Wire(3, 1), in = new Wire(8, 1);\r
-               in.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
-               new Splitter(in.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               in.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+               new Splitter(in.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(), c.createReadWriteEnd());\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -72,11 +72,11 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(2, 1), c = new Wire(3, 1), out = new Wire(8, 1);\r
-               a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO);\r
-               b.createEnd().feedSignals(Bit.ONE, Bit.ZERO);\r
-               c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
+               a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO);\r
+               b.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO);\r
+               c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
-               new Merger(out.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
+               new Merger(out.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -87,11 +87,11 @@ class ComponentTest
        void triStateBufferTest()\r
        {\r
                Wire a = new Wire(1, 1), b = new Wire(1, 1), en = new Wire(1, 1), notEn = new Wire(1, 1);\r
-               new NotGate(1, en.createReadOnlyEnd(), notEn.createEnd());\r
-               new TriStateBuffer(1, a.createReadOnlyEnd(), b.createEnd(), en.createReadOnlyEnd());\r
-               new TriStateBuffer(1, b.createReadOnlyEnd(), a.createEnd(), notEn.createReadOnlyEnd());\r
+               new NotGate(1, en.createReadOnlyEnd(), notEn.createReadWriteEnd());\r
+               new TriStateBuffer(1, a.createReadOnlyEnd(), b.createReadWriteEnd(), en.createReadOnlyEnd());\r
+               new TriStateBuffer(1, b.createReadOnlyEnd(), a.createReadWriteEnd(), notEn.createReadOnlyEnd());\r
 \r
-               ReadWriteEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd();\r
+               ReadWriteEnd enI = en.createReadWriteEnd(), aI = a.createReadWriteEnd(), bI = b.createReadWriteEnd();\r
                enI.feedSignals(Bit.ONE);\r
                aI.feedSignals(Bit.ONE);\r
                bI.feedSignals(Bit.Z);\r
@@ -121,13 +121,13 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), out = new Wire(4, 1);\r
-               ReadWriteEnd selectIn = select.createEnd();\r
+               ReadWriteEnd selectIn = select.createReadWriteEnd();\r
 \r
                selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
-               a.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
-               c.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+               a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
+               c.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
-               new Mux(1, out.createEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
+               new Mux(1, out.createReadWriteEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
                Simulation.TIMELINE.executeAll();\r
 \r
                assertBitArrayEquals(out.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
@@ -148,12 +148,12 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), in = new Wire(4, 1);\r
-               ReadWriteEnd selectIn = select.createEnd();\r
+               ReadWriteEnd selectIn = select.createReadWriteEnd();\r
 \r
                selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
-               in.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
+               in.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
 \r
-               new Demux(1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Demux(1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(), c.createReadWriteEnd());\r
                Simulation.TIMELINE.executeAll();\r
 \r
                assertBitArrayEquals(a.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
@@ -180,9 +180,9 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1);\r
-               new AndGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
-               a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
-               b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+               new AndGate(1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
+               a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+               b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -194,9 +194,9 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1);\r
-               new OrGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
-               a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
-               b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+               new OrGate(1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
+               a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+               b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -208,10 +208,10 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(3, 2), c = new Wire(3, 1), d = new Wire(3, 1);\r
-               new XorGate(1, d.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
-               a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
-               b.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
-               c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
+               new XorGate(1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
+               a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
+               b.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
+               c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -223,8 +223,8 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(3, 2);\r
-               new NotGate(1, a.createReadOnlyEnd(), b.createEnd());\r
-               a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
+               new NotGate(1, a.createReadOnlyEnd(), b.createReadWriteEnd());\r
+               a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -237,12 +237,12 @@ class ComponentTest
                Simulation.TIMELINE.reset();\r
                Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1), q = new Wire(1, 1), nq = new Wire(1, 1);\r
 \r
-               new OrGate(1, t2.createEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd());\r
-               new OrGate(1, t1.createEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd());\r
-               new NotGate(1, t2.createReadOnlyEnd(), q.createEnd());\r
-               new NotGate(1, t1.createReadOnlyEnd(), nq.createEnd());\r
+               new OrGate(1, t2.createReadWriteEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd());\r
+               new OrGate(1, t1.createReadWriteEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd());\r
+               new NotGate(1, t2.createReadOnlyEnd(), q.createReadWriteEnd());\r
+               new NotGate(1, t1.createReadOnlyEnd(), nq.createReadWriteEnd());\r
 \r
-               ReadWriteEnd sIn = s.createEnd(), rIn = r.createEnd();\r
+               ReadWriteEnd sIn = s.createReadWriteEnd(), rIn = r.createReadWriteEnd();\r
 \r
                sIn.feedSignals(Bit.ONE);\r
                rIn.feedSignals(Bit.ZERO);\r
@@ -272,7 +272,7 @@ class ComponentTest
                Simulation.TIMELINE.reset();\r
 \r
                Wire a = new Wire(4, 1);\r
-               a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ONE, Bit.ONE);\r
+               a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ONE, Bit.ONE);\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -285,7 +285,7 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire w = new Wire(2, 1);\r
-               ReadWriteEnd wI1 = w.createEnd(), wI2 = w.createEnd();\r
+               ReadWriteEnd wI1 = w.createReadWriteEnd(), wI2 = w.createReadWriteEnd();\r
                wI1.feedSignals(Bit.ONE, Bit.Z);\r
                wI2.feedSignals(Bit.Z, Bit.X);\r
                Simulation.TIMELINE.executeAll();\r
@@ -321,9 +321,9 @@ class ComponentTest
                Wire a = new Wire(1, 2);\r
                Wire b = new Wire(1, 2);\r
                Wire c = new Wire(1, 2);\r
-               ReadWriteEnd aI = a.createEnd();\r
-               ReadWriteEnd bI = b.createEnd();\r
-               ReadWriteEnd cI = c.createEnd();\r
+               ReadWriteEnd aI = a.createReadWriteEnd();\r
+               ReadWriteEnd bI = b.createReadWriteEnd();\r
+               ReadWriteEnd cI = c.createReadWriteEnd();\r
 \r
                TestBitDisplay test = new TestBitDisplay(c.createReadOnlyEnd());\r
                TestBitDisplay test2 = new TestBitDisplay(a.createReadOnlyEnd());\r
@@ -339,7 +339,7 @@ class ComponentTest
                cI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
 \r
-               new Connector(b.createEnd(), c.createEnd()).connect();\r
+               new Connector(b.createReadWriteEnd(), c.createReadWriteEnd()).connect();\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
                System.err.println("ONE");\r
                bI.feedSignals(Bit.ONE);\r
@@ -351,7 +351,7 @@ class ComponentTest
                bI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
 \r
-               new Connector(a.createEnd(), b.createEnd()).connect();\r
+               new Connector(a.createReadWriteEnd(), b.createReadWriteEnd()).connect();\r
                System.err.println("Z 2");\r
                aI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r

diff --git a/era.mi/src/era/mi/logic/tests/GUITest.java b/era.mi/src/era/mi/logic/tests/GUITest.java
index 814a3b7..8ff7384 100644 (file)
--- a/era.mi/src/era/mi/logic/tests/GUITest.java
+++ b/era.mi/src/era/mi/logic/tests/GUITest.java
@@ -38,13 +38,13 @@ public class GUITest extends JPanel
        Wire q = new Wire(1, WIRE_DELAY);\r
        Wire nq = new Wire(1, WIRE_DELAY);\r
 \r
-       ManualSwitch rIn = new ManualSwitch(r.createEnd());\r
-       ManualSwitch sIn = new ManualSwitch(s.createEnd());\r
+       ManualSwitch rIn = new ManualSwitch(r.createReadWriteEnd());\r
+       ManualSwitch sIn = new ManualSwitch(s.createReadWriteEnd());\r
 \r
-       OrGate or1 = new OrGate(OR_DELAY, t2.createEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd());\r
-       OrGate or2 = new OrGate(OR_DELAY, t1.createEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd());\r
-       NotGate not1 = new NotGate(NOT_DELAY, t2.createReadOnlyEnd(), q.createEnd());\r
-       NotGate not2 = new NotGate(NOT_DELAY, t1.createReadOnlyEnd(), nq.createEnd());\r
+       OrGate or1 = new OrGate(OR_DELAY, t2.createReadWriteEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd());\r
+       OrGate or2 = new OrGate(OR_DELAY, t1.createReadWriteEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd());\r
+       NotGate not1 = new NotGate(NOT_DELAY, t2.createReadOnlyEnd(), q.createReadWriteEnd());\r
+       NotGate not2 = new NotGate(NOT_DELAY, t1.createReadOnlyEnd(), nq.createReadWriteEnd());\r
 \r
        Map<ManualSwitch, Rectangle> switchMap = new HashMap<>();\r
 \r

diff --git a/era.mi/src/era/mi/logic/wires/Wire.java b/era.mi/src/era/mi/logic/wires/Wire.java
index 5eaf27a..3a71a36 100644 (file)
--- a/era.mi/src/era/mi/logic/wires/Wire.java
+++ b/era.mi/src/era/mi/logic/wires/Wire.java
@@ -189,7 +189,7 @@ public class Wire
        /**\r
         * Create and register a {@link ReadWriteEnd} object, which is tied to this {@link Wire}. This {@link ReadWriteEnd} can be written to.\r
         */\r
-       public ReadWriteEnd createEnd()\r
+       public ReadWriteEnd createReadWriteEnd()\r
        {\r
                return new ReadWriteEnd();\r
        }\r
@@ -484,7 +484,7 @@ public class Wire
        {\r
                ReadEnd[] inputs = new ReadEnd[w.length];\r
                for (int i = 0; i < w.length; i++)\r
-                       inputs[i] = w[i].createEnd();\r
+                       inputs[i] = w[i].createReadWriteEnd();\r
                return inputs;\r
        }\r
 }
\ No newline at end of file