From: Daniel Kirschten <daniel.kirschten@gmx.de>
Date: Sun, 1 Mar 2020 16:26:28 +0000 (+0100)
Subject: VerilogExporter now "hands through" a clk signal
X-Git-Url: https://mograsim.net/gitweb/?a=commitdiff_plain;h=0072642bcbf00c26d9a96796257c0caec0390e22;p=Mograsim.git

VerilogExporter now "hands through" a clk signal

to avoid combinatorial loops
---

diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
index e1d60bc5..daef1aac 100644
--- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
+++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
@@ -305,7 +305,7 @@ public class VerilogExporter
 
 	private void appendInterface(StringBuilder result)
 	{
-		result.append("input rst");
+		result.append("input rst, input clk");
 		if (!sortedInterfacePinNames.isEmpty())
 		{
 			Map<String, Integer> logicWidthsPerInterfacePinName = Arrays.stream(componentJson.interfacePins)
@@ -430,7 +430,7 @@ public class VerilogExporter
 			result.append(' ');
 			// abuse the pinIdentifierGenerator for making these unique
 			result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
-			result.append(" (rst");
+			result.append(" (rst, clk");
 			for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
 			{
 				result.append(",\n  ");