From: Daniel Kirschten Date: Sun, 15 Sep 2019 12:33:31 +0000 (+0200) Subject: Applied formatter to all source files X-Git-Url: https://mograsim.net/gitweb/?a=commitdiff_plain;h=14e2ce1a88c70f0835a80639c085611236dd135f;p=Mograsim.git Applied formatter to all source files --- diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreComponent.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreComponent.java index 85d39e8a..734f48de 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreComponent.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreComponent.java @@ -16,8 +16,8 @@ public abstract class CoreComponent } /** - * Returns immutable list of all inputs to the {@link CoreComponent} (including e.g. the select bits to a MUX). Intended for visualization - * in the UI. + * Returns immutable list of all inputs to the {@link CoreComponent} (including e.g. the select bits to a MUX). Intended for + * visualization in the UI. */ public abstract List getAllInputs(); diff --git a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/CoreComponentTest.java b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/CoreComponentTest.java index 3b670472..ebebd6bf 100644 --- a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/CoreComponentTest.java +++ b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/CoreComponentTest.java @@ -40,9 +40,9 @@ class CoreComponentTest @Test void circuitExampleTest() { - CoreWire a = new CoreWire(t, 1, 1), b = new CoreWire(t, 1, 1), c = new CoreWire(t, 1, 10), d = new CoreWire(t, 2, 1), e = new CoreWire(t, 1, 1), - f = new CoreWire(t, 1, 1), g = new CoreWire(t, 1, 1), h = new CoreWire(t, 2, 1), i = new CoreWire(t, 2, 1), j = new CoreWire(t, 1, 1), - k = new CoreWire(t, 1, 1); + CoreWire a = new CoreWire(t, 1, 1), b = new CoreWire(t, 1, 1), c = new CoreWire(t, 1, 10), d = new CoreWire(t, 2, 1), + e = new CoreWire(t, 1, 1), f = new CoreWire(t, 1, 1), g = new CoreWire(t, 1, 1), h = new CoreWire(t, 2, 1), + i = new CoreWire(t, 2, 1), j = new CoreWire(t, 1, 1), k = new CoreWire(t, 1, 1); new CoreAndGate(t, 1, f.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); new CoreNotGate(t, 1, f.createReadOnlyEnd(), g.createReadWriteEnd()); new CoreUnidirectionalMerger(t, h.createReadWriteEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd()); @@ -205,7 +205,8 @@ class CoreComponentTest @Test void muxTest() { - CoreWire a = new CoreWire(t, 4, 3), b = new CoreWire(t, 4, 6), c = new CoreWire(t, 4, 4), select = new CoreWire(t, 2, 5), out = new CoreWire(t, 4, 1); + CoreWire a = new CoreWire(t, 4, 3), b = new CoreWire(t, 4, 6), c = new CoreWire(t, 4, 4), select = new CoreWire(t, 2, 5), + out = new CoreWire(t, 4, 1); ReadWriteEnd selectIn = select.createReadWriteEnd(); selectIn.feedSignals(Bit.ZERO, Bit.ZERO); @@ -232,7 +233,8 @@ class CoreComponentTest @Test void demuxTest() { - CoreWire a = new CoreWire(t, 4, 3), b = new CoreWire(t, 4, 6), c = new CoreWire(t, 4, 4), select = new CoreWire(t, 2, 5), in = new CoreWire(t, 4, 1); + CoreWire a = new CoreWire(t, 4, 3), b = new CoreWire(t, 4, 6), c = new CoreWire(t, 4, 4), select = new CoreWire(t, 2, 5), + in = new CoreWire(t, 4, 1); ReadWriteEnd selectIn = select.createReadWriteEnd(); selectIn.feedSignals(Bit.ZERO, Bit.ZERO); @@ -344,8 +346,8 @@ class CoreComponentTest @Test void rsLatchCircuitTest() { - CoreWire r = new CoreWire(t, 1, 1), s = new CoreWire(t, 1, 1), t1 = new CoreWire(t, 1, 15), t2 = new CoreWire(t, 1, 1), q = new CoreWire(t, 1, 1), - nq = new CoreWire(t, 1, 1); + CoreWire r = new CoreWire(t, 1, 1), s = new CoreWire(t, 1, 1), t1 = new CoreWire(t, 1, 15), t2 = new CoreWire(t, 1, 1), + q = new CoreWire(t, 1, 1), nq = new CoreWire(t, 1, 1); new CoreOrGate(t, 1, t2.createReadWriteEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd()); new CoreOrGate(t, 1, t1.createReadWriteEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd()); diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/ModelWire.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/ModelWire.java index 6d45c7ba..1f44f570 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/ModelWire.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/ModelWire.java @@ -257,8 +257,8 @@ public class ModelWire } /** - * Destroys this wire. This method is called from {@link LogicModelModifiable#wireDestroyed(ModelWire) wireDestroyed()} of the model this - * wire is a part of. + * Destroys this wire. This method is called from {@link LogicModelModifiable#wireDestroyed(ModelWire) wireDestroyed()} of the model + * this wire is a part of. * * @author Daniel Kirschten */ diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/NoLogicAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/NoLogicAdapter.java index 3cc859eb..ea87e78e 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/NoLogicAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/NoLogicAdapter.java @@ -29,8 +29,7 @@ public class NoLogicAdapter implements ComponentAdapte } @Override - public void createAndLinkComponent(Timeline timeline, CoreModelParameters params, T modelComponent, - Map logicWiresPerPin) + public void createAndLinkComponent(Timeline timeline, CoreModelParameters params, T modelComponent, Map logicWiresPerPin) { // do nothing } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java index 72008e1c..c38883e6 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java @@ -29,8 +29,7 @@ public class SimpleGateAdapter implements } @Override - public void createAndLinkComponent(Timeline timeline, CoreModelParameters params, G modelComponent, - Map logicWiresPerPin) + public void createAndLinkComponent(Timeline timeline, CoreModelParameters params, G modelComponent, Map logicWiresPerPin) { ReadWriteEnd out = logicWiresPerPin.get(modelComponent.getPin("Y")).createReadWriteEnd();