From: Christian Femers <femers@in.tum.de>
Date: Mon, 26 Aug 2019 01:03:45 +0000 (+0200)
Subject: Refactored Wire and finally renamed length to width
X-Git-Url: https://mograsim.net/gitweb/?a=commitdiff_plain;h=3e6ac3d7fd389191d02c1c6982fbf093421ce4f2;hp=3e6ac3d7fd389191d02c1c6982fbf093421ce4f2;p=Mograsim.git

Refactored Wire and finally renamed length to width

Note: since this change was prolonged for some time, so it needed to be changed in a lot of places. The reason for the renaming is the confusability with the length of a (e.g. physical) wire. But it is more precise to call it (bit-) width, since the length of a BitVector passing through the wire becomes its width. (This seems to be similar named in Verilog)
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