From: Daniel Kirschten Date: Mon, 4 May 2020 18:24:53 +0000 (+0200) Subject: Implemented the Am2904ShiftInstrDecode gate-based X-Git-Url: https://mograsim.net/gitweb/?a=commitdiff_plain;h=d1bac6997196c2921e33307d9061908b938b80f8;p=Mograsim.git Implemented the Am2904ShiftInstrDecode gate-based --- diff --git a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904ShiftInstrDecode.json b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904ShiftInstrDecode.json new file mode 100644 index 00000000..66b33461 --- /dev/null +++ b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904ShiftInstrDecode.json @@ -0,0 +1,4322 @@ +{ + "width": 60.0, + "height": 80.0, + "interfacePins": [ + { + "location": { + "x": 0.0, + "y": 25.0 + }, + "name": "I", + "logicWidth": 5, + "usage": "OUTPUT" + }, + { + "location": { + "x": 60.0, + "y": 75.0 + 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30.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#14", + "pinName": "" + }, + "pin2": { + "compName": "NandGate#0", + "pinName": "B" + }, + "name": "unnamedWire#165", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#44", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#48", + "pinName": "" + }, + "name": "unnamedWire#166", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#36", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#46", + "pinName": "" + }, + "name": "unnamedWire#167", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#39", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#24", + "pinName": "" + }, + "name": "unnamedWire#168", + "path": [ + { + "x": 80.0, + "y": 225.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#40", + "pinName": "" + }, + "pin2": { + "compName": "and#1", + "pinName": "B" + }, + "name": "unnamedWire#169", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#41", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#57", + "pinName": "" + }, + "name": "unnamedWire#170", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#42", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#53", + "pinName": "" + }, + "name": "unnamedWire#171", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#43", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#52", + "pinName": "" + }, + "name": "unnamedWire#172", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#35", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#44", + "pinName": "" + }, + "name": "unnamedWire#173", + "path": [ + { + "x": 40.0, + "y": 220.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#45", + "pinName": "" + }, + "pin2": { + "compName": "NandGate#21", + "pinName": "A" + }, + "name": "unnamedWire#174", + "path": [ + { + "x": 180.0, + "y": 80.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#46", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#47", + "pinName": "" + }, + "name": "unnamedWire#175", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#47", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#62", + "pinName": "" + }, + "name": "unnamedWire#176", + "path": [ + { + "x": 330.0, + "y": 280.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#48", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#60", + "pinName": "" + }, + "name": "unnamedWire#177", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#52", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#16", + "pinName": "" + }, + "name": "unnamedWire#178", + "path": [ + { + "x": 470.0, + "y": 230.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#47", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#50", + "pinName": "" + }, + "name": "unnamedWire#179", + "path": [ + { + "x": 330.0, + "y": 90.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#51", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#15", + "pinName": "" + }, + "name": "unnamedWire#180", + "path": [ + { + "x": 345.0, + "y": 60.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#52", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#49", + "pinName": "" + }, + "name": "unnamedWire#181", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#53", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#12", + "pinName": "" + }, + "name": "unnamedWire#182", + "path": [ + { + "x": 360.0, + "y": 165.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#12", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#54", + "pinName": "" + }, + "name": "unnamedWire#183", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#55", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#21", + "pinName": "" + }, + "name": "unnamedWire#184", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#57", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#8", + "pinName": "" + }, + "name": "unnamedWire#185", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#56", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#57", + "pinName": "" + }, + "name": "unnamedWire#186", + "path": [ + { + "x": 365.0, + "y": 155.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#21", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#23", + "pinName": "" + }, + "name": "unnamedWire#187", + "path": [ + { + "x": 340.0, + "y": 320.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#59", + "pinName": "" + }, + "pin2": { + "compName": "NandGate#10", + "pinName": "B" + }, + "name": "unnamedWire#188", + "path": [ + { + "x": 370.0, + "y": 175.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#8", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#20", + "pinName": "" + }, + "name": "unnamedWire#189", + "path": [] + }, + { + "pin1": { + "compName": "WireCrossPoint#61", + "pinName": "" + }, + "pin2": { + "compName": "NandGate#25", + "pinName": "B" + }, + "name": "unnamedWire#190", + "path": [ + { + "x": 490.0, + "y": 235.0 + } + ] + }, + { + "pin1": { + "compName": "WireCrossPoint#62", + "pinName": "" + }, + "pin2": { + "compName": "WireCrossPoint#6", + "pinName": "" + }, + "name": "unnamedWire#191", + "path": [] + } + ], + "version": "0.1.1" + }, + "symbolRendererSnippetID": "simpleRectangularLike", + "symbolRendererParams": { + "centerText": "Shift\nInstruction\ndecode", + "centerTextHeight": 5.0, + "horizontalComponentCenter": 30.0, + "pinLabelHeight": 3.5, + "pinLabelMargin": 0.5 + }, + "outlineRendererSnippetID": "default", + "highLevelStateHandlerSnippetID": "default", + "version": "0.1.5" +} \ No newline at end of file diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/ModelAm2904ShiftInstrDecode.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/ModelAm2904ShiftInstrDecode.java deleted file mode 100644 index e2329f56..00000000 --- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/ModelAm2904ShiftInstrDecode.java +++ /dev/null @@ -1,323 +0,0 @@ -package net.mograsim.logic.model.am2900.components.am2904; - -import static net.mograsim.logic.core.types.Bit.ONE; -import static net.mograsim.logic.core.types.Bit.U; -import static net.mograsim.logic.core.types.Bit.X; -import static net.mograsim.logic.core.types.Bit.Z; -import static net.mograsim.logic.core.types.Bit.ZERO; - -import java.util.Map; - -import net.mograsim.logic.core.types.Bit; -import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.CoreWire.ReadEnd; -import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; -import net.mograsim.logic.model.model.LogicModelModifiable; -import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedModelComponent; -import net.mograsim.logic.model.model.wires.Pin; -import net.mograsim.logic.model.model.wires.PinUsage; -import net.mograsim.logic.model.serializing.IndirectModelComponentCreator; -import net.mograsim.logic.model.snippets.symbolrenderers.PinNamesSymbolRenderer.PinNamesParams.Position; - -public class ModelAm2904ShiftInstrDecode extends SimpleRectangularHardcodedModelComponent -{ - public ModelAm2904ShiftInstrDecode(LogicModelModifiable model, String name) - { - super(model, "Am2904ShiftInstrDecode", name, "Shift \ninstruction\ndecode", false); - setSize(60, 80); - addPin(new Pin(model, this, "I", 5, PinUsage.INPUT, 0, 25), Position.RIGHT); - addPin(new Pin(model, this, "_SE", 1, PinUsage.INPUT, 0, 55), Position.RIGHT); - // SIO0 MUX: - // 000: 0 - // 001: 1 - // 01x: SIOn - // 10x: QIOn - // 11x: MC - addPin(new Pin(model, this, "SIO0_MUX", 3, PinUsage.OUTPUT, 60, 5), Position.LEFT); - // SIOn MUX: - // 000: 0 - // 001: 1 - // 010: SIO0 - // 011: QIO0 - // 100: MC - // 101: MN - // 110: IC - // 111: IN xor IVOR - addPin(new Pin(model, this, "SIOn_MUX", 3, PinUsage.OUTPUT, 60, 15), Position.LEFT); - // QIO0 MUX: - // 000: 0 - // 001: 1 - // 01x: SIOn - // 10x: QIOn - // 11x: MC - addPin(new Pin(model, this, "QIO0_MUX", 3, PinUsage.OUTPUT, 60, 25), Position.LEFT); - // QIOn MUX: - // 000: 0 - // 001: 1 - // 01x: SIO0 - // 10x: QIO0 - // 11x: MN - addPin(new Pin(model, this, "QIOn_MUX", 3, PinUsage.OUTPUT, 60, 35), Position.LEFT); - addPin(new Pin(model, this, "OEn", 1, PinUsage.OUTPUT, 60, 45), Position.LEFT); - addPin(new Pin(model, this, "OE0", 1, PinUsage.OUTPUT, 60, 55), Position.LEFT); - // 00: SIO0 - // 01: QIO0 - // 1x: SIOn - addPin(new Pin(model, this, "MC_MUX", 2, PinUsage.OUTPUT, 60, 65), Position.LEFT); - addPin(new Pin(model, this, "MC_EN", 1, PinUsage.OUTPUT, 60, 75), Position.LEFT); - - init(); - } - - @Override - public Object recalculate(Object lastState, Map readEnds, Map readWriteEnds) - { - Bit _SE = readEnds.get("_SE").getValue(); - BitVector I = readEnds.get("I").getValues(); - readWriteEnds.get("OEn").feedSignals(I.getMSBit(0).not().and(_SE.not())); - readWriteEnds.get("OE0").feedSignals(I.getMSBit(0).and(_SE.not())); - if (_SE == Z || _SE == X) - { - readWriteEnds.get("SIO0_MUX").feedSignals(X, X, X); - readWriteEnds.get("SIOn_MUX").feedSignals(X, X, X); - readWriteEnds.get("QIO0_MUX").feedSignals(X, X, X); - readWriteEnds.get("QIOn_MUX").feedSignals(X, X, X); - readWriteEnds.get("MC_MUX").feedSignals(X, X); - readWriteEnds.get("MC_EN").feedSignals(X); - return null; - } else if (_SE == U) - { - - readWriteEnds.get("SIO0_MUX").feedSignals(U, U, U); - readWriteEnds.get("SIOn_MUX").feedSignals(U, U, U); - readWriteEnds.get("QIO0_MUX").feedSignals(U, U, U); - readWriteEnds.get("QIOn_MUX").feedSignals(U, U, U); - readWriteEnds.get("MC_MUX").feedSignals(U, U); - readWriteEnds.get("MC_EN").feedSignals(U); - return null; - } else if (_SE == ONE) - { - readWriteEnds.get("SIO0_MUX").feedSignals(X, X, X); - readWriteEnds.get("SIOn_MUX").feedSignals(X, X, X); - readWriteEnds.get("QIO0_MUX").feedSignals(X, X, X); - readWriteEnds.get("QIOn_MUX").feedSignals(X, X, X); - readWriteEnds.get("MC_MUX").feedSignals(X, X); - readWriteEnds.get("MC_EN").feedSignals(ZERO); - return null; - } - if (!I.isBinary()) - { - Bit val = null; - for (Bit b : I.getBits()) - if (!b.isBinary()) - { - val = b; - break; - } - readWriteEnds.get("SIO0_MUX").feedSignals(val, val, val); - readWriteEnds.get("SIOn_MUX").feedSignals(val, val, val); - readWriteEnds.get("QIO0_MUX").feedSignals(val, val, val); - readWriteEnds.get("QIOn_MUX").feedSignals(val, val, val); - readWriteEnds.get("MC_MUX").feedSignals(val, val); - readWriteEnds.get("MC_EN").feedSignals(val); - return null; - } - int IAsInt = I.getUnsignedValue().intValue(); - if (IAsInt < 16) - { - readWriteEnds.get("SIO0_MUX").feedSignals(X, X, X); - readWriteEnds.get("QIO0_MUX").feedSignals(X, X, X); - switch (IAsInt) - { - case 0: - case 2: - case 6: - case 7: - readWriteEnds.get("SIOn_MUX").feedSignals(ZERO, ZERO, ZERO); - break; - case 1: - case 3: - readWriteEnds.get("SIOn_MUX").feedSignals(ZERO, ZERO, ONE); - break; - case 4: - case 9: - case 12: - readWriteEnds.get("SIOn_MUX").feedSignals(ONE, ZERO, ZERO); - break; - case 5: - readWriteEnds.get("SIOn_MUX").feedSignals(ONE, ZERO, ONE); - break; - case 8: - case 10: - readWriteEnds.get("SIOn_MUX").feedSignals(ZERO, ONE, ZERO); - break; - case 11: - readWriteEnds.get("SIOn_MUX").feedSignals(ONE, ONE, ZERO); - break; - case 13: - case 15: - readWriteEnds.get("SIOn_MUX").feedSignals(ZERO, ONE, ONE); - break; - case 14: - readWriteEnds.get("SIOn_MUX").feedSignals(ONE, ONE, ONE); - break; - default: - throw new IllegalStateException("can't happen"); - } - switch (IAsInt) - { - case 0: - readWriteEnds.get("QIOn_MUX").feedSignals(ZERO, ZERO, ZERO); - break; - case 1: - readWriteEnds.get("QIOn_MUX").feedSignals(ZERO, ZERO, ONE); - break; - case 2: - readWriteEnds.get("QIOn_MUX").feedSignals(ONE, ONE, X); - break; - case 3: - case 4: - case 5: - case 6: - case 7: - case 11: - case 12: - case 13: - case 14: - case 15: - readWriteEnds.get("QIOn_MUX").feedSignals(ZERO, ONE, X); - break; - case 8: - case 9: - case 10: - readWriteEnds.get("QIOn_MUX").feedSignals(ONE, ZERO, X); - break; - default: - throw new IllegalStateException("can't happen"); - } - } else - { - readWriteEnds.get("SIOn_MUX").feedSignals(X, X, X); - readWriteEnds.get("QIOn_MUX").feedSignals(X, X, X); - switch (IAsInt) - { - case 16: - case 18: - readWriteEnds.get("SIO0_MUX").feedSignals(ZERO, ZERO, ZERO); - break; - case 17: - case 19: - readWriteEnds.get("SIO0_MUX").feedSignals(ZERO, ZERO, ONE); - break; - case 20: - case 21: - case 22: - case 23: - case 28: - case 29: - case 30: - case 31: - readWriteEnds.get("SIO0_MUX").feedSignals(ONE, ZERO, X); - break; - case 24: - case 26: - readWriteEnds.get("SIO0_MUX").feedSignals(ZERO, ONE, X); - break; - case 25: - case 27: - readWriteEnds.get("SIO0_MUX").feedSignals(ONE, ONE, X); - break; - default: - throw new IllegalStateException("can't happen"); - } - switch (IAsInt) - { - case 16: - case 18: - case 20: - case 22: - case 27: - readWriteEnds.get("QIO0_MUX").feedSignals(ZERO, ZERO, ZERO); - break; - case 17: - case 19: - case 21: - case 23: - readWriteEnds.get("QIO0_MUX").feedSignals(ZERO, ZERO, ONE); - break; - case 24: - case 25: - case 26: - readWriteEnds.get("QIO0_MUX").feedSignals(ONE, ZERO, X); - break; - case 28: - case 30: - readWriteEnds.get("QIO0_MUX").feedSignals(ONE, ONE, X); - break; - case 29: - case 31: - readWriteEnds.get("QIO0_MUX").feedSignals(ZERO, ONE, X); - break; - default: - throw new IllegalStateException("can't happen"); - } - } - // MC - switch (IAsInt) - { - case 0: - case 1: - case 3: - case 4: - case 5: - case 6: - case 10: - case 11: - case 14: - case 15: - case 18: - case 19: - case 22: - case 23: - case 26: - case 27: - case 30: - case 31: - readWriteEnds.get("MC_EN").feedSignals(ZERO); - readWriteEnds.get("MC_MUX").feedSignals(X, X); - break; - case 2: - case 8: - case 9: - readWriteEnds.get("MC_EN").feedSignals(ONE); - readWriteEnds.get("MC_MUX").feedSignals(ZERO, ZERO); - break; - case 7: - case 12: - case 13: - readWriteEnds.get("MC_EN").feedSignals(ONE); - readWriteEnds.get("MC_MUX").feedSignals(ZERO, ONE); - break; - case 16: - case 17: - case 20: - case 21: - case 24: - case 25: - case 28: - case 29: - readWriteEnds.get("MC_EN").feedSignals(ONE); - readWriteEnds.get("MC_MUX").feedSignals(ONE, X); - break; - default: - throw new IllegalStateException("can't happen"); - } - return null; - } - - static - { - IndirectModelComponentCreator.setComponentSupplier(ModelAm2904ShiftInstrDecode.class.getCanonicalName(), - (m, p, n) -> new ModelAm2904ShiftInstrDecode(m, n)); - } -} \ No newline at end of file diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/standardComponentIDMapping.json b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/standardComponentIDMapping.json index 3b94540b..a3c0728f 100644 --- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/standardComponentIDMapping.json +++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/standardComponentIDMapping.json @@ -1,7 +1,6 @@ { "Am2900MainMemory": "resloader:Am2900Loader:class:net.mograsim.logic.model.am2900.components.ModelAm2900MainMemory", "Am2900MicroInstructionMemory": "resloader:Am2900Loader:class:net.mograsim.logic.model.am2900.components.ModelAm2900MicroInstructionMemory", - "Am2904ShiftInstrDecode": "resloader:Am2900Loader:class:net.mograsim.logic.model.am2900.components.am2904.ModelAm2904ShiftInstrDecode", "ram5_12": "resloader:Am2900Loader:class:net.mograsim.logic.model.am2900.components.Modelram5_12", "Am2900": "resloader:Am2900Loader:jsonres:net/mograsim/logic/model/am2900/components/Am2900.json", @@ -17,6 +16,7 @@ "Am2904MSR": "resloader:Am2900Loader:jsonres:net/mograsim/logic/model/am2900/components/am2904/Am2904MSR.json", "Am2904muSR": "resloader:Am2900Loader:jsonres:net/mograsim/logic/model/am2900/components/am2904/Am2904muSR.json", "Am2904RegCTInstrDecode": "resloader:Am2900Loader:jsonres:net/mograsim/logic/model/am2900/components/am2904/Am2904RegCTInstrDecode.json", + "Am2904ShiftInstrDecode": "resloader:Am2900Loader:jsonres:net/mograsim/logic/model/am2900/components/am2904/Am2904ShiftInstrDecode.json", "Am2904TestLogic": "resloader:Am2900Loader:jsonres:net/mograsim/logic/model/am2900/components/am2904/Am2904TestLogic.json", "Am2910": "resloader:Am2900Loader:jsonres:net/mograsim/logic/model/am2900/components/am2910/Am2910.json", "Am2910InstrPLA": "resloader:Am2900Loader:jsonres:net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json",