From 253f4e92e8a8b644ef5fa2343adc3088954822ee Mon Sep 17 00:00:00 2001 From: Daniel Kirschten Date: Mon, 15 Mar 2021 16:38:48 +0100 Subject: [PATCH] Handing through rst and clk signals (still very ugly) --- .../model/verilog/model/VerilogComponentImplementation.java | 5 ++++- .../model/verilog/model/statements/ComponentReference.java | 3 ++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java index a7a9de29..3dead220 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java @@ -58,7 +58,10 @@ public class VerilogComponentImplementation StringBuilder sb = new StringBuilder(); sb.append("module " + declaration.getID()); - sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode).collect(Collectors.joining(", ", "(", ")"))); + // TODO handle rst / clk more cleanly. + // Also in CompenentReference + sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode) + .collect(Collectors.joining(", ", "(input rst,input clk,", ")"))); sb.append(";\n\n"); for (Statement statement : statements) diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java index dcce7606..94a214e6 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java @@ -59,7 +59,8 @@ public class ComponentReference extends Statement StringBuilder sb = new StringBuilder(); sb.append(referencedComponent.getID() + " " + name); - sb.append(arguments.stream().map(Expression::toVerilogCode).collect(Collectors.joining(", ", "(", ")"))); + // TODO handle rst / clk more cleanly; see VerilogCompenentImplementation + sb.append(arguments.stream().map(Expression::toVerilogCode).collect(Collectors.joining(", ", "(rst,clk,", ")"))); sb.append(";"); return sb.toString(); -- 2.17.1