From 0072642bcbf00c26d9a96796257c0caec0390e22 Mon Sep 17 00:00:00 2001 From: Daniel Kirschten Date: Sun, 1 Mar 2020 17:26:28 +0100 Subject: [PATCH] VerilogExporter now "hands through" a clk signal to avoid combinatorial loops --- .../net/mograsim/logic/model/examples/VerilogExporter.java | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java index e1d60bc5..daef1aac 100644 --- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java +++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java @@ -305,7 +305,7 @@ public class VerilogExporter private void appendInterface(StringBuilder result) { - result.append("input rst"); + result.append("input rst, input clk"); if (!sortedInterfacePinNames.isEmpty()) { Map logicWidthsPerInterfacePinName = Arrays.stream(componentJson.interfacePins) @@ -430,7 +430,7 @@ public class VerilogExporter result.append(' '); // abuse the pinIdentifierGenerator for making these unique result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName)); - result.append(" (rst"); + result.append(" (rst, clk"); for (int i = 0; i < subcomponentInterfacePinNames.size(); i++) { result.append(",\n "); -- 2.17.1