From 0a04a4ed66ecebd4254541c4977599f6052c115a Mon Sep 17 00:00:00 2001 From: Daniel Kirschten Date: Thu, 5 Sep 2019 17:28:32 +0200 Subject: [PATCH] Renamed core components to have the common prefix Core --- ...Component.java => BasicCoreComponent.java} | 4 +- .../logic/core/components/Component.java | 28 ---- .../{BitDisplay.java => CoreBitDisplay.java} | 8 +- .../components/{Clock.java => CoreClock.java} | 12 +- .../logic/core/components/CoreComponent.java | 28 ++++ .../components/{Demux.java => CoreDemux.java} | 14 +- ...anualSwitch.java => CoreManualSwitch.java} | 8 +- .../components/{Mux.java => CoreMux.java} | 14 +- ...ateBuffer.java => CoreTriStateBuffer.java} | 8 +- ...ger.java => CoreUnidirectionalMerger.java} | 12 +- ...r.java => CoreUnidirectionalSplitter.java} | 8 +- .../logic/core/components/gates/AndGate.java | 14 -- .../core/components/gates/CoreAndGate.java | 14 ++ .../core/components/gates/CoreNandGate.java | 14 ++ .../core/components/gates/CoreNorGate.java | 14 ++ .../gates/{NotGate.java => CoreNotGate.java} | 10 +- .../core/components/gates/CoreOrGate.java | 14 ++ .../gates/{XorGate.java => CoreXorGate.java} | 8 +- ...InputGate.java => MultiInputCoreGate.java} | 12 +- .../logic/core/components/gates/NandGate.java | 14 -- .../logic/core/components/gates/NorGate.java | 14 -- .../logic/core/components/gates/OrGate.java | 14 -- .../logic/core/types/BitVectorFormatter.java | 2 +- .../core/wires/{Wire.java => CoreWire.java} | 116 ++++++++-------- ...ponentTest.java => CoreComponentTest.java} | 130 +++++++++--------- .../mograsim/logic/core/tests/GUITest.java | 44 +++--- ...itDisplay.java => TestCoreBitDisplay.java} | 8 +- .../model/am2900/components/GUIdff12.java | 4 +- .../am2900/components/GUIdff4_finewe.java | 4 +- .../model/am2900/components/GUIinc12.java | 4 +- .../model/am2900/components/GUInor12.java | 4 +- .../model/am2900/components/GUIram5_12.java | 4 +- .../model/am2900/components/GUIsel4_12.java | 4 +- .../am2904/GUIAm2904RegCTInstrDecode.java | 4 +- .../am2904/GUIAm2904ShiftInstrDecode.java | 4 +- .../components/am2910/GUIAm2910InstrPLA.java | 4 +- .../components/am2910/GUIAm2910RegCntr.java | 4 +- .../am2900/components/am2910/GUIAm2910SP.java | 4 +- .../model/am2900/machine/Am2900Machine.java | 6 +- .../am2900/am2901/TestableAm2901Impl.java | 20 +-- .../am2900/am2904/TestableAm2904Impl.java | 24 ++-- .../am2900/am2910/TestableAm2910Impl.java | 26 ++-- .../model/am2900/util/SwitchWithDisplay.java | 8 +- .../am2900/util/TestEnvironmentHelper.java | 8 +- .../model/editor/handles/WirePointHandle.java | 4 +- .../model/components/atomic/GUIAndGate.java | 4 +- .../components/atomic/GUIBitDisplay.java | 8 +- .../model/components/atomic/GUIClock.java | 8 +- .../components/atomic/GUIManualSwitch.java | 8 +- .../model/components/atomic/GUIMerger.java | 2 +- .../model/components/atomic/GUINandGate.java | 4 +- .../model/components/atomic/GUINotGate.java | 4 +- .../model/components/atomic/GUIOrGate.java | 4 +- .../model/components/atomic/GUISplitter.java | 2 +- ...impleRectangularHardcodedGUIComponent.java | 4 +- .../logic/model/model/wires/GUIWire.java | 6 +- .../model/model/wires/WireCrossPoint.java | 2 +- .../modeladapter/ViewLogicModelAdapter.java | 40 +++--- .../componentadapters/BitDisplayAdapter.java | 10 +- .../componentadapters/ClockAdapter.java | 10 +- .../componentadapters/ComponentAdapter.java | 4 +- .../componentadapters/FixedOutputAdapter.java | 4 +- .../ManualSwitchAdapter.java | 10 +- .../componentadapters/MergerAdapter.java | 12 +- .../componentadapters/NoLogicAdapter.java | 4 +- .../componentadapters/SimpleGateAdapter.java | 12 +- ...ctangularHardcodedGUIComponentAdapter.java | 10 +- .../componentadapters/SplitterAdapter.java | 12 +- .../TriStateBufferAdapter.java | 12 +- .../src/net/mograsim/machine/Machine.java | 4 +- .../memory/WordAddressableMemoryAdapter.java | 8 +- .../WordAddressableMemoryComponent.java | 8 +- .../memory/WordAddressableMemoryTest.java | 10 +- 73 files changed, 476 insertions(+), 476 deletions(-) rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{BasicComponent.java => BasicCoreComponent.java} (83%) delete mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/Component.java rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{BitDisplay.java => CoreBitDisplay.java} (83%) rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{Clock.java => CoreClock.java} (79%) create mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreComponent.java rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{Demux.java => CoreDemux.java} (80%) rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{ManualSwitch.java => CoreManualSwitch.java} (88%) rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{Mux.java => CoreMux.java} (81%) rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{TriStateBuffer.java => CoreTriStateBuffer.java} (78%) rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{UnidirectionalMerger.java => CoreUnidirectionalMerger.java} (76%) rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/{UnidirectionalSplitter.java => CoreUnidirectionalSplitter.java} (80%) delete mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/AndGate.java create mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreAndGate.java create mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNandGate.java create mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNorGate.java rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/{NotGate.java => CoreNotGate.java} (66%) create mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreOrGate.java rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/{XorGate.java => CoreXorGate.java} (56%) rename net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/{MultiInputGate.java => MultiInputCoreGate.java} (72%) delete mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NandGate.java delete mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NorGate.java delete mode 100644 net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/OrGate.java rename net.mograsim.logic.core/src/net/mograsim/logic/core/wires/{Wire.java => CoreWire.java} (79%) rename net.mograsim.logic.core/test/net/mograsim/logic/core/tests/{ComponentTest.java => CoreComponentTest.java} (65%) rename net.mograsim.logic.core/test/net/mograsim/logic/core/tests/{TestBitDisplay.java => TestCoreBitDisplay.java} (78%) diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/BasicComponent.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/BasicCoreComponent.java similarity index 83% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/BasicComponent.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/BasicCoreComponent.java index 56dc6875..9f3da4a2 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/BasicComponent.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/BasicCoreComponent.java @@ -9,7 +9,7 @@ import net.mograsim.logic.core.timeline.Timeline; * * @author Fabian Stemmler */ -public abstract class BasicComponent extends Component implements LogicObserver +public abstract class BasicCoreComponent extends CoreComponent implements LogicObserver { private int processTime; @@ -19,7 +19,7 @@ public abstract class BasicComponent extends Component implements LogicObserver * * @author Fabian Stemmler */ - public BasicComponent(Timeline timeline, int processTime) + public BasicCoreComponent(Timeline timeline, int processTime) { super(timeline); this.processTime = processTime > 0 ? processTime : 1; diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Component.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Component.java deleted file mode 100644 index 834f4b5b..00000000 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Component.java +++ /dev/null @@ -1,28 +0,0 @@ -package net.mograsim.logic.core.components; - -import java.util.List; - -import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; - -public abstract class Component -{ - protected Timeline timeline; - - public Component(Timeline timeline) - { - this.timeline = timeline; - } - - /** - * Returns immutable list of all inputs to the {@link Component} (including e.g. the select bits to a MUX). Intended for visualization - * in the UI. - */ - public abstract List getAllInputs(); - - /** - * Returns immutable list of all outputs to the {@link Component}. Intended for visualization in the UI. - */ - public abstract List getAllOutputs(); -} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/BitDisplay.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreBitDisplay.java similarity index 83% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/BitDisplay.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreBitDisplay.java index 799f4124..8cd509c4 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/BitDisplay.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreBitDisplay.java @@ -9,16 +9,16 @@ import net.mograsim.logic.core.LogicObserver; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; -public class BitDisplay extends BasicComponent implements LogicObservable +public class CoreBitDisplay extends BasicCoreComponent implements LogicObservable { private Collection observers; private final ReadEnd in; private BitVector displayedValue; - public BitDisplay(Timeline timeline, ReadEnd in) + public CoreBitDisplay(Timeline timeline, ReadEnd in) { super(timeline, 1); observers = new ArrayList<>(); diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Clock.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreClock.java similarity index 79% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/Clock.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreClock.java index b691d7e7..0cccdfdd 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Clock.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreClock.java @@ -10,11 +10,11 @@ import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.timeline.TimelineEvent; import net.mograsim.logic.core.timeline.TimelineEventHandler; import net.mograsim.logic.core.types.Bit; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; -public class Clock extends Component implements TimelineEventHandler, LogicObservable +public class CoreClock extends CoreComponent implements TimelineEventHandler, LogicObservable { private Collection observers; private boolean toggle = false; @@ -23,10 +23,10 @@ public class Clock extends Component implements TimelineEventHandler, LogicObser /** * - * @param out {@link Wire} the clock's impulses are fed into + * @param out {@link CoreWire} the clock's impulses are fed into * @param delta ticks between rising and falling edge */ - public Clock(Timeline timeline, ReadWriteEnd out, int delta) + public CoreClock(Timeline timeline, ReadWriteEnd out, int delta) { super(timeline); this.delta = delta; diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreComponent.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreComponent.java new file mode 100644 index 00000000..85d39e8a --- /dev/null +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreComponent.java @@ -0,0 +1,28 @@ +package net.mograsim.logic.core.components; + +import java.util.List; + +import net.mograsim.logic.core.timeline.Timeline; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; + +public abstract class CoreComponent +{ + protected Timeline timeline; + + public CoreComponent(Timeline timeline) + { + this.timeline = timeline; + } + + /** + * Returns immutable list of all inputs to the {@link CoreComponent} (including e.g. the select bits to a MUX). Intended for visualization + * in the UI. + */ + public abstract List getAllInputs(); + + /** + * Returns immutable list of all outputs to the {@link CoreComponent}. Intended for visualization in the UI. + */ + public abstract List getAllOutputs(); +} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Demux.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreDemux.java similarity index 80% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/Demux.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreDemux.java index 5cf80747..a5bb0fc6 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Demux.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreDemux.java @@ -3,18 +3,18 @@ package net.mograsim.logic.core.components; import java.util.List; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; /** - * Models a multiplexer. Takes an arbitrary amount of input {@link Wire}s, one of which, as determined by select, is put through to the + * Models a multiplexer. Takes an arbitrary amount of input {@link CoreWire}s, one of which, as determined by select, is put through to the * output. * * @author Fabian Stemmler * */ -public class Demux extends BasicComponent +public class CoreDemux extends BasicCoreComponent { private final ReadEnd select, in; private final ReadWriteEnd[] outputs; @@ -22,13 +22,13 @@ public class Demux extends BasicComponent private int selected = -1; /** - * Output {@link Wire}s and in must be of uniform width + * Output {@link CoreWire}s and in must be of uniform width * * @param in Must be of uniform width with all outputs. * @param select Indexes the output array to which the input is mapped. Must have enough bits to index all outputs. * @param outputs One of these outputs receives the input signal, depending on the select bits */ - public Demux(Timeline timeline, int processTime, ReadEnd in, ReadEnd select, ReadWriteEnd... outputs) + public CoreDemux(Timeline timeline, int processTime, ReadEnd in, ReadEnd select, ReadWriteEnd... outputs) { super(timeline, processTime); outputSize = in.width(); diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/ManualSwitch.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreManualSwitch.java similarity index 88% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/ManualSwitch.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreManualSwitch.java index fa31f0c6..b7e5d3a6 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/ManualSwitch.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreManualSwitch.java @@ -9,8 +9,8 @@ import net.mograsim.logic.core.LogicObserver; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; /** * This class models a simple on/off (ONE/ZERO) switch for user interaction. @@ -18,13 +18,13 @@ import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; * @author Christian Femers * */ -public class ManualSwitch extends Component implements LogicObservable +public class CoreManualSwitch extends CoreComponent implements LogicObservable { private Collection observers; private ReadWriteEnd output; private BitVector inputValues; - public ManualSwitch(Timeline timeline, ReadWriteEnd output) + public CoreManualSwitch(Timeline timeline, ReadWriteEnd output) { super(timeline); observers = new ArrayList<>(); diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Mux.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreMux.java similarity index 81% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/Mux.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreMux.java index 3776bde9..b85168d6 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/Mux.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreMux.java @@ -6,18 +6,18 @@ import java.util.Collections; import java.util.List; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; /** - * Models a multiplexer. Takes an arbitrary amount of input {@link Wire}s, one of which, as determined by select, is put through to the + * Models a multiplexer. Takes an arbitrary amount of input {@link CoreWire}s, one of which, as determined by select, is put through to the * output. * * @author Fabian Stemmler * */ -public class Mux extends BasicComponent +public class CoreMux extends BasicCoreComponent { private ReadEnd select; private ReadWriteEnd out; @@ -25,13 +25,13 @@ public class Mux extends BasicComponent private final int outputSize; /** - * Input {@link Wire}s and out must be of uniform width + * Input {@link CoreWire}s and out must be of uniform width * * @param out Must be of uniform width with all inputs. * @param select Indexes the input array which is to be mapped to the output. Must have enough bits to index all inputs. * @param inputs One of these inputs is mapped to the output, depending on the select bits */ - public Mux(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd select, ReadEnd... inputs) + public CoreMux(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd select, ReadEnd... inputs) { super(timeline, processTime); outputSize = out.width(); diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/TriStateBuffer.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreTriStateBuffer.java similarity index 78% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/TriStateBuffer.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreTriStateBuffer.java index 057c49e5..6568d1bf 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/TriStateBuffer.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreTriStateBuffer.java @@ -4,15 +4,15 @@ import java.util.List; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.Bit; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; -public class TriStateBuffer extends BasicComponent +public class CoreTriStateBuffer extends BasicCoreComponent { ReadEnd in, enable; ReadWriteEnd out; - public TriStateBuffer(Timeline timeline, int processTime, ReadEnd in, ReadWriteEnd out, ReadEnd enable) + public CoreTriStateBuffer(Timeline timeline, int processTime, ReadEnd in, ReadWriteEnd out, ReadEnd enable) { super(timeline, processTime); if (in.width() != out.width()) diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/UnidirectionalMerger.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalMerger.java similarity index 76% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/UnidirectionalMerger.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalMerger.java index f1c3f8bc..6e6b0f15 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/UnidirectionalMerger.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalMerger.java @@ -5,11 +5,11 @@ import java.util.List; import net.mograsim.logic.core.LogicObservable; import net.mograsim.logic.core.LogicObserver; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; -public class UnidirectionalMerger extends Component implements LogicObserver +public class CoreUnidirectionalMerger extends CoreComponent implements LogicObserver { private ReadWriteEnd out; private ReadEnd[] inputs; @@ -17,10 +17,10 @@ public class UnidirectionalMerger extends Component implements LogicObserver /** * - * @param union The output of merging n {@link Wire}s into one. Must have width = a1.width() + a2.width() + ... + an.width(). + * @param union The output of merging n {@link CoreWire}s into one. Must have width = a1.width() + a2.width() + ... + an.width(). * @param inputs The inputs to be merged into the union */ - public UnidirectionalMerger(Timeline timeline, ReadWriteEnd union, ReadEnd... inputs) + public CoreUnidirectionalMerger(Timeline timeline, ReadWriteEnd union, ReadEnd... inputs) { super(timeline); this.inputs = inputs; diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/UnidirectionalSplitter.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalSplitter.java similarity index 80% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/UnidirectionalSplitter.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalSplitter.java index 13816adb..d77e1541 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/UnidirectionalSplitter.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreUnidirectionalSplitter.java @@ -6,15 +6,15 @@ import net.mograsim.logic.core.LogicObservable; import net.mograsim.logic.core.LogicObserver; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; -public class UnidirectionalSplitter extends Component implements LogicObserver +public class CoreUnidirectionalSplitter extends CoreComponent implements LogicObserver { private ReadEnd input; private ReadWriteEnd[] outputs; - public UnidirectionalSplitter(Timeline timeline, ReadEnd input, ReadWriteEnd... outputs) + public CoreUnidirectionalSplitter(Timeline timeline, ReadEnd input, ReadWriteEnd... outputs) { super(timeline); this.input = input; diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/AndGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/AndGate.java deleted file mode 100644 index fa1e94b6..00000000 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/AndGate.java +++ /dev/null @@ -1,14 +0,0 @@ -package net.mograsim.logic.core.components.gates; - -import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.types.BitVector.BitVectorMutator; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; - -public class AndGate extends MultiInputGate -{ - public AndGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) - { - super(timeline, processTime, BitVectorMutator::and, out, in); - } -} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreAndGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreAndGate.java new file mode 100644 index 00000000..d71e08e1 --- /dev/null +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreAndGate.java @@ -0,0 +1,14 @@ +package net.mograsim.logic.core.components.gates; + +import net.mograsim.logic.core.timeline.Timeline; +import net.mograsim.logic.core.types.BitVector.BitVectorMutator; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; + +public class CoreAndGate extends MultiInputCoreGate +{ + public CoreAndGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) + { + super(timeline, processTime, BitVectorMutator::and, out, in); + } +} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNandGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNandGate.java new file mode 100644 index 00000000..e847d0ec --- /dev/null +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNandGate.java @@ -0,0 +1,14 @@ +package net.mograsim.logic.core.components.gates; + +import net.mograsim.logic.core.timeline.Timeline; +import net.mograsim.logic.core.types.BitVector.BitVectorMutator; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; + +public class CoreNandGate extends MultiInputCoreGate +{ + public CoreNandGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) + { + super(timeline, processTime, BitVectorMutator::and, true, out, in); + } +} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNorGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNorGate.java new file mode 100644 index 00000000..12336274 --- /dev/null +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNorGate.java @@ -0,0 +1,14 @@ +package net.mograsim.logic.core.components.gates; + +import net.mograsim.logic.core.timeline.Timeline; +import net.mograsim.logic.core.types.BitVector.BitVectorMutator; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; + +public class CoreNorGate extends MultiInputCoreGate +{ + public CoreNorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) + { + super(timeline, processTime, BitVectorMutator::or, true, out, in); + } +} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NotGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNotGate.java similarity index 66% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NotGate.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNotGate.java index 14fe85d6..57f3a187 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NotGate.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreNotGate.java @@ -2,17 +2,17 @@ package net.mograsim.logic.core.components.gates; import java.util.List; -import net.mograsim.logic.core.components.BasicComponent; +import net.mograsim.logic.core.components.BasicCoreComponent; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; -public class NotGate extends BasicComponent +public class CoreNotGate extends BasicCoreComponent { private ReadEnd in; private ReadWriteEnd out; - public NotGate(Timeline timeline, int processTime, ReadEnd in, ReadWriteEnd out) + public CoreNotGate(Timeline timeline, int processTime, ReadEnd in, ReadWriteEnd out) { super(timeline, processTime); this.in = in; diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreOrGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreOrGate.java new file mode 100644 index 00000000..97d75c80 --- /dev/null +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreOrGate.java @@ -0,0 +1,14 @@ +package net.mograsim.logic.core.components.gates; + +import net.mograsim.logic.core.timeline.Timeline; +import net.mograsim.logic.core.types.BitVector.BitVectorMutator; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; + +public class CoreOrGate extends MultiInputCoreGate +{ + public CoreOrGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) + { + super(timeline, processTime, BitVectorMutator::or, out, in); + } +} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/XorGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreXorGate.java similarity index 56% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/XorGate.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreXorGate.java index 15c24e27..8bc98934 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/XorGate.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreXorGate.java @@ -2,17 +2,17 @@ package net.mograsim.logic.core.components.gates; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.BitVector.BitVectorMutator; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; /** * Outputs 1 when the number of 1 inputs is odd. * * @author Fabian Stemmler */ -public class XorGate extends MultiInputGate +public class CoreXorGate extends MultiInputCoreGate { - public XorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) + public CoreXorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) { super(timeline, processTime, BitVectorMutator::xor, out, in); } diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputCoreGate.java similarity index 72% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputCoreGate.java index d7fecc19..59fc3cdc 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputCoreGate.java @@ -2,14 +2,14 @@ package net.mograsim.logic.core.components.gates; import java.util.List; -import net.mograsim.logic.core.components.BasicComponent; +import net.mograsim.logic.core.components.BasicCoreComponent; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.BitVector.BitVectorMutator; import net.mograsim.logic.core.types.MutationOperation; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; -public abstract class MultiInputGate extends BasicComponent +public abstract class MultiInputCoreGate extends BasicCoreComponent { protected ReadEnd[] in; protected ReadWriteEnd out; @@ -17,7 +17,7 @@ public abstract class MultiInputGate extends BasicComponent protected MutationOperation op; protected boolean invert = false; - protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, ReadWriteEnd out, ReadEnd... in) + protected MultiInputCoreGate(Timeline timeline, int processTime, MutationOperation op, ReadWriteEnd out, ReadEnd... in) { super(timeline, processTime); this.op = op; @@ -34,7 +34,7 @@ public abstract class MultiInputGate extends BasicComponent this.out = out; } - protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, boolean invert, ReadWriteEnd out, ReadEnd... in) + protected MultiInputCoreGate(Timeline timeline, int processTime, MutationOperation op, boolean invert, ReadWriteEnd out, ReadEnd... in) { this(timeline, processTime, op, out, in); this.invert = invert; diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NandGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NandGate.java deleted file mode 100644 index 0e40648e..00000000 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NandGate.java +++ /dev/null @@ -1,14 +0,0 @@ -package net.mograsim.logic.core.components.gates; - -import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.types.BitVector.BitVectorMutator; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; - -public class NandGate extends MultiInputGate -{ - public NandGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) - { - super(timeline, processTime, BitVectorMutator::and, true, out, in); - } -} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NorGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NorGate.java deleted file mode 100644 index 5f6e185e..00000000 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NorGate.java +++ /dev/null @@ -1,14 +0,0 @@ -package net.mograsim.logic.core.components.gates; - -import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.types.BitVector.BitVectorMutator; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; - -public class NorGate extends MultiInputGate -{ - public NorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) - { - super(timeline, processTime, BitVectorMutator::or, true, out, in); - } -} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/OrGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/OrGate.java deleted file mode 100644 index 0072d506..00000000 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/OrGate.java +++ /dev/null @@ -1,14 +0,0 @@ -package net.mograsim.logic.core.components.gates; - -import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.types.BitVector.BitVectorMutator; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; - -public class OrGate extends MultiInputGate -{ - public OrGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in) - { - super(timeline, processTime, BitVectorMutator::or, out, in); - } -} diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/types/BitVectorFormatter.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/types/BitVectorFormatter.java index c551fed9..5f645a2e 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/types/BitVectorFormatter.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/types/BitVectorFormatter.java @@ -1,6 +1,6 @@ package net.mograsim.logic.core.types; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.preferences.ColorDefinition; import net.mograsim.preferences.ColorDefinition.BuiltInColor; import net.mograsim.preferences.Preferences; diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/wires/Wire.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/wires/CoreWire.java similarity index 79% rename from net.mograsim.logic.core/src/net/mograsim/logic/core/wires/Wire.java rename to net.mograsim.logic.core/src/net/mograsim/logic/core/wires/CoreWire.java index 15755ae9..f643f8ec 100644 --- a/net.mograsim.logic.core/src/net/mograsim/logic/core/wires/Wire.java +++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/wires/CoreWire.java @@ -20,7 +20,7 @@ import net.mograsim.logic.core.types.BitVector.BitVectorMutator; * @author Fabian Stemmler * */ -public class Wire +public class CoreWire { public final String name; private BitVector cachedValues; @@ -32,12 +32,12 @@ public class Wire private Bit[] bitsWithoutFusions; FusedBit[] fusedBits; - public Wire(Timeline timeline, int width, int travelTime) + public CoreWire(Timeline timeline, int width, int travelTime) { this(timeline, width, travelTime, null); } - public Wire(Timeline timeline, int width, int travelTime, String name) + public CoreWire(Timeline timeline, int width, int travelTime, String name) { if (width < 1) throw new IllegalArgumentException( @@ -126,7 +126,7 @@ public class Wire } /** - * The {@link Wire} is interpreted as an unsigned integer with n bits. + * The {@link CoreWire} is interpreted as an unsigned integer with n bits. * * @return true if all bits are either Bit.ONE or Bit.ZERO (they do not all have to have the same * value), not Bit.U, Bit.X or Bit.Z. false is returned otherwise. @@ -139,9 +139,9 @@ public class Wire } /** - * The {@link Wire} is interpreted as an unsigned integer with n bits. + * The {@link CoreWire} is interpreted as an unsigned integer with n bits. * - * @return The unsigned value of the {@link Wire}'s bits, where value 0 corresponds with 2^0, value 1 is 2^1 and so on. + * @return The unsigned value of the {@link CoreWire}'s bits, where value 0 corresponds with 2^0, value 1 is 2^1 and so on. * * @author Fabian Stemmler */ @@ -168,9 +168,9 @@ public class Wire } /** - * The {@link Wire} is interpreted as a signed integer with n bits. + * The {@link CoreWire} is interpreted as a signed integer with n bits. * - * @return The signed value of the {@link Wire}'s bits, where value 0 corresponds with 2^0, value 1 is 2^1 and so on. + * @return The signed value of the {@link CoreWire}'s bits, where value 0 corresponds with 2^0, value 1 is 2^1 and so on. * * @author Fabian Stemmler */ @@ -215,7 +215,7 @@ public class Wire } /** - * Adds an {@link LogicObserver}, who will be notified when the value of the {@link Wire} is updated. + * Adds an {@link LogicObserver}, who will be notified when the value of the {@link CoreWire} is updated. * * @param ob The {@link LogicObserver} to be notified of changes. * @return true if the given {@link LogicObserver} was not already registered, false otherwise @@ -238,7 +238,7 @@ public class Wire } /** - * Create and register a {@link ReadWriteEnd} object, which is tied to this {@link Wire}. This {@link ReadWriteEnd} can be written to. + * Create and register a {@link ReadWriteEnd} object, which is tied to this {@link CoreWire}. This {@link ReadWriteEnd} can be written to. */ public ReadWriteEnd createReadWriteEnd() { @@ -246,7 +246,7 @@ public class Wire } /** - * Create a {@link ReadEnd} object, which is tied to this {@link Wire}. This {@link ReadEnd} cannot be written to. + * Create a {@link ReadEnd} object, which is tied to this {@link CoreWire}. This {@link ReadEnd} cannot be written to. */ public ReadEnd createReadOnlyEnd() { @@ -260,8 +260,8 @@ public class Wire } /** - * A {@link ReadEnd} feeds a constant signal into the {@link Wire} it is tied to. The combination of all inputs determines the - * {@link Wire}s final value. X dominates all other inputs Z does not affect the final value, unless there are no other inputs than Z 0 + * A {@link ReadEnd} feeds a constant signal into the {@link CoreWire} it is tied to. The combination of all inputs determines the + * {@link CoreWire}s final value. X dominates all other inputs Z does not affect the final value, unless there are no other inputs than Z 0 * and 1 turn into X when they are mixed * * @author Fabian Stemmler @@ -273,7 +273,7 @@ public class Wire ReadEnd() { super(); - Wire.this.attachEnd(this); + CoreWire.this.attachEnd(this); } public void update() @@ -282,7 +282,7 @@ public class Wire } /** - * Included for convenient use on {@link Wire}s of width 1. + * Included for convenient use on {@link CoreWire}s of width 1. * * @return The value of bit 0. * @@ -290,7 +290,7 @@ public class Wire */ public Bit getValue() { - return Wire.this.getValue(); + return CoreWire.this.getValue(); } /** @@ -301,12 +301,12 @@ public class Wire */ public Bit getValue(int index) { - return Wire.this.getValue(index); + return CoreWire.this.getValue(index); } public BitVector getValues() { - return Wire.this.getValues(); + return CoreWire.this.getValues(); } /** @@ -318,11 +318,11 @@ public class Wire */ public BitVector getValues(int start, int end) { - return Wire.this.getValues(start, end); + return CoreWire.this.getValues(start, end); } /** - * The {@link Wire} is interpreted as an unsigned integer with n bits. + * The {@link CoreWire} is interpreted as an unsigned integer with n bits. * * @return true if all bits are either Bit.ONE or Bit.ZERO (they do not all have to have the * same value), not Bit.X or Bit.Z. false is returned otherwise. @@ -331,37 +331,37 @@ public class Wire */ public boolean hasNumericValue() { - return Wire.this.hasNumericValue(); + return CoreWire.this.hasNumericValue(); } /** - * The {@link Wire} is interpreted as an unsigned integer with n bits. + * The {@link CoreWire} is interpreted as an unsigned integer with n bits. * - * @return The unsigned value of the {@link Wire}'s bits, where value 0 corresponds with 2^0, value 1 is 2^1 and so on. + * @return The unsigned value of the {@link CoreWire}'s bits, where value 0 corresponds with 2^0, value 1 is 2^1 and so on. * * @author Fabian Stemmler */ public long getUnsignedValue() { - return Wire.this.getUnsignedValue(); + return CoreWire.this.getUnsignedValue(); } /** - * The {@link Wire} is interpreted as a signed integer with n bits. + * The {@link CoreWire} is interpreted as a signed integer with n bits. * - * @return The signed value of the {@link Wire}'s bits, where value 0 corresponds with 2^0, value 1 is 2^1 and so on. + * @return The signed value of the {@link CoreWire}'s bits, where value 0 corresponds with 2^0, value 1 is 2^1 and so on. * * @author Fabian Stemmler */ public long getSignedValue() { - return Wire.this.getSignedValue(); + return CoreWire.this.getSignedValue(); } @Override public String toString() { - return Wire.this.toString(); + return CoreWire.this.toString(); } public void close() @@ -376,9 +376,9 @@ public class Wire return width; } - public Wire getWire() + public CoreWire getWire() { - return Wire.this; + return CoreWire.this; } @Override @@ -431,7 +431,7 @@ public class Wire } /** - * Sets the wires values. This takes up time, as specified by the {@link Wire}s travel time. + * Sets the wires values. This takes up time, as specified by the {@link CoreWire}s travel time. * * @param newValues The new values the wires should take on. * @@ -453,7 +453,7 @@ public class Wire } /** - * Sets values of a subarray of wires. This takes up time, as specified by the {@link Wire}s travel time. + * Sets values of a subarray of wires. This takes up time, as specified by the {@link CoreWire}s travel time. * * @param bitVector The new values the wires should take on. * @param startingBit The first index of the subarray of wires. @@ -468,7 +468,7 @@ public class Wire } /** - * Sets the values that are being fed into the {@link Wire}. The preferred way of setting {@link ReadWriteEnd} values is via + * Sets the values that are being fed into the {@link CoreWire}. The preferred way of setting {@link ReadWriteEnd} values is via * feedValues(...) with a delay. */ void setValues(int startingBit, BitVector newValues) @@ -479,12 +479,12 @@ public class Wire Bit[] vals = inputValues.getBits(); System.arraycopy(newValues.getBits(), 0, vals, startingBit, newValues.length()); inputValues = BitVector.of(vals); - Wire.this.recalculateValuesWithoutFusions(); + CoreWire.this.recalculateValuesWithoutFusions(); } } /** - * Sets the values that are being fed into the {@link Wire}. The preferred way of setting {@link ReadWriteEnd} values is via + * Sets the values that are being fed into the {@link CoreWire}. The preferred way of setting {@link ReadWriteEnd} values is via * feedValues(...) with a delay. */ void setValues(BitVector newValues) @@ -492,11 +492,11 @@ public class Wire if (inputValues.equals(newValues)) return; inputValues = newValues; - Wire.this.recalculateValuesWithoutFusions(); + CoreWire.this.recalculateValuesWithoutFusions(); } /** - * @return The value (of bit 0) the {@link ReadEnd} is currently feeding into the associated {@link Wire}.Returns the least + * @return The value (of bit 0) the {@link ReadEnd} is currently feeding into the associated {@link CoreWire}.Returns the least * significant bit (LSB) */ public Bit getInputValue() @@ -505,7 +505,7 @@ public class Wire } /** - * @return The value which the {@link ReadEnd} is currently feeding into the associated {@link Wire} at the indexed {@link Bit}. + * @return The value which the {@link ReadEnd} is currently feeding into the associated {@link CoreWire} at the indexed {@link Bit}. * Returns the least significant bit (LSB) * */ @@ -515,7 +515,7 @@ public class Wire } /** - * @return A copy (safe to modify) of the values the {@link ReadEnd} is currently feeding into the associated {@link Wire}. + * @return A copy (safe to modify) of the values the {@link ReadEnd} is currently feeding into the associated {@link CoreWire}. */ public BitVector getInputValues() { @@ -528,7 +528,7 @@ public class Wire } /** - * {@link ReadEnd} now feeds Z into the associated {@link Wire}. + * {@link ReadEnd} now feeds Z into the associated {@link CoreWire}. */ public void clearSignals() { @@ -573,7 +573,7 @@ public class Wire inputs.add(this); else inputs.remove(this); - Wire.this.recalculateValuesWithoutFusions(); + CoreWire.this.recalculateValuesWithoutFusions(); } } @@ -590,7 +590,7 @@ public class Wire return String.format("wire %s value: %s inputs: %s", name, getValues(), inputs); } - public static ReadEnd[] extractEnds(Wire[] w) + public static ReadEnd[] extractEnds(CoreWire[] w) { ReadEnd[] inputs = new ReadEnd[w.length]; for (int i = 0; i < w.length; i++) @@ -603,10 +603,10 @@ public class Wire * Fuses two wires together. If the bits change in one Wire, the other is changed accordingly immediately. Warning: The bits are * permanently fused together. * - * @param a The {@link Wire} to be fused with b - * @param b The {@link Wire} to be fused with a + * @param a The {@link CoreWire} to be fused with b + * @param b The {@link CoreWire} to be fused with a */ - public static void fuse(Wire a, Wire b) + public static void fuse(CoreWire a, CoreWire b) { fuse(a, b, 0, 0, a.width); } @@ -615,13 +615,13 @@ public class Wire * Fuses the selected bits of two wires together. If the bits change in one Wire, the other is changed accordingly immediately. Warning: * The bits are permanently fused together. * - * @param a The {@link Wire} to be (partially) fused with b - * @param b The {@link Wire} to be (partially) fused with a - * @param fromA The first bit of {@link Wire} a to be fused - * @param fromB The first bit of {@link Wire} b to be fused + * @param a The {@link CoreWire} to be (partially) fused with b + * @param b The {@link CoreWire} to be (partially) fused with a + * @param fromA The first bit of {@link CoreWire} a to be fused + * @param fromB The first bit of {@link CoreWire} b to be fused * @param width The amount of bits to fuse */ - public static void fuse(Wire a, Wire b, int fromA, int fromB, int width) + public static void fuse(CoreWire a, CoreWire b, int fromA, int fromB, int width) { // iterate in this direction to be fail-fast (rely on the checks in fuse(Wire, Wire, int, int) for (int i = width - 1; i >= 0; i--) @@ -632,12 +632,12 @@ public class Wire * Fuses one bit of two wires together. If this bit changes in one Wire, the other is changed accordingly immediately. Warning: The bits * are permanently fused together. * - * @param a The {@link Wire} to be (partially) fused with b - * @param b The {@link Wire} to be (partially) fused with a - * @param bitA The bit of {@link Wire} a to be fused - * @param bitB The bit of {@link Wire} b to be fused + * @param a The {@link CoreWire} to be (partially) fused with b + * @param b The {@link CoreWire} to be (partially) fused with a + * @param bitA The bit of {@link CoreWire} a to be fused + * @param bitB The bit of {@link CoreWire} b to be fused */ - public static void fuse(Wire a, Wire b, int bitA, int bitB) + public static void fuse(CoreWire a, CoreWire b, int bitA, int bitB) { if (bitA >= a.width) throw new IllegalArgumentException("No bit " + bitA + " in " + a + " (width " + a.width + ")"); @@ -672,7 +672,7 @@ public class Wire this.participatingWireBits = new ArrayList<>(); } - public void addParticipatingWireBit(Wire w, int bit) + public void addParticipatingWireBit(CoreWire w, int bit) { addParticipatingWireBit(new WireBit(w, bit)); } @@ -711,10 +711,10 @@ public class Wire private static class WireBit { - public final Wire wire; + public final CoreWire wire; public final int bit; - public WireBit(Wire wire, int bit) + public WireBit(CoreWire wire, int bit) { this.wire = wire; this.bit = bit; diff --git a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/ComponentTest.java b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/CoreComponentTest.java similarity index 65% rename from net.mograsim.logic.core/test/net/mograsim/logic/core/tests/ComponentTest.java rename to net.mograsim.logic.core/test/net/mograsim/logic/core/tests/CoreComponentTest.java index 464db587..3b670472 100644 --- a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/ComponentTest.java +++ b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/CoreComponentTest.java @@ -8,26 +8,26 @@ import org.junit.jupiter.api.BeforeEach; import org.junit.jupiter.api.Disabled; import org.junit.jupiter.api.Test; -import net.mograsim.logic.core.components.Demux; -import net.mograsim.logic.core.components.Mux; -import net.mograsim.logic.core.components.TriStateBuffer; -import net.mograsim.logic.core.components.UnidirectionalMerger; -import net.mograsim.logic.core.components.UnidirectionalSplitter; -import net.mograsim.logic.core.components.gates.AndGate; -import net.mograsim.logic.core.components.gates.NandGate; -import net.mograsim.logic.core.components.gates.NorGate; -import net.mograsim.logic.core.components.gates.NotGate; -import net.mograsim.logic.core.components.gates.OrGate; -import net.mograsim.logic.core.components.gates.XorGate; +import net.mograsim.logic.core.components.CoreDemux; +import net.mograsim.logic.core.components.CoreMux; +import net.mograsim.logic.core.components.CoreTriStateBuffer; +import net.mograsim.logic.core.components.CoreUnidirectionalMerger; +import net.mograsim.logic.core.components.CoreUnidirectionalSplitter; +import net.mograsim.logic.core.components.gates.CoreAndGate; +import net.mograsim.logic.core.components.gates.CoreNandGate; +import net.mograsim.logic.core.components.gates.CoreNorGate; +import net.mograsim.logic.core.components.gates.CoreNotGate; +import net.mograsim.logic.core.components.gates.CoreOrGate; +import net.mograsim.logic.core.components.gates.CoreXorGate; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; @SuppressWarnings("unused") -class ComponentTest +class CoreComponentTest { private Timeline t = new Timeline(11); @@ -40,14 +40,14 @@ class ComponentTest @Test void circuitExampleTest() { - Wire a = new Wire(t, 1, 1), b = new Wire(t, 1, 1), c = new Wire(t, 1, 10), d = new Wire(t, 2, 1), e = new Wire(t, 1, 1), - f = new Wire(t, 1, 1), g = new Wire(t, 1, 1), h = new Wire(t, 2, 1), i = new Wire(t, 2, 1), j = new Wire(t, 1, 1), - k = new Wire(t, 1, 1); - new AndGate(t, 1, f.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); - new NotGate(t, 1, f.createReadOnlyEnd(), g.createReadWriteEnd()); - new UnidirectionalMerger(t, h.createReadWriteEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd()); - new Mux(t, 1, i.createReadWriteEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd()); - new UnidirectionalSplitter(t, i.createReadOnlyEnd(), k.createReadWriteEnd(), j.createReadWriteEnd()); + CoreWire a = new CoreWire(t, 1, 1), b = new CoreWire(t, 1, 1), c = new CoreWire(t, 1, 10), d = new CoreWire(t, 2, 1), e = new CoreWire(t, 1, 1), + f = new CoreWire(t, 1, 1), g = new CoreWire(t, 1, 1), h = new CoreWire(t, 2, 1), i = new CoreWire(t, 2, 1), j = new CoreWire(t, 1, 1), + k = new CoreWire(t, 1, 1); + new CoreAndGate(t, 1, f.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); + new CoreNotGate(t, 1, f.createReadOnlyEnd(), g.createReadWriteEnd()); + new CoreUnidirectionalMerger(t, h.createReadWriteEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd()); + new CoreMux(t, 1, i.createReadWriteEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd()); + new CoreUnidirectionalSplitter(t, i.createReadOnlyEnd(), k.createReadWriteEnd(), j.createReadWriteEnd()); a.createReadWriteEnd().feedSignals(Bit.ZERO); b.createReadWriteEnd().feedSignals(Bit.ONE); @@ -64,9 +64,9 @@ class ComponentTest @Test void splitterTest() { - Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), in = new Wire(t, 8, 1); + CoreWire a = new CoreWire(t, 3, 1), b = new CoreWire(t, 2, 1), c = new CoreWire(t, 3, 1), in = new CoreWire(t, 8, 1); in.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); - new UnidirectionalSplitter(t, in.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(), c.createReadWriteEnd()); + new CoreUnidirectionalSplitter(t, in.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(), c.createReadWriteEnd()); t.executeAll(); @@ -78,12 +78,12 @@ class ComponentTest @Test void mergerTest() { - Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), out = new Wire(t, 8, 1); + CoreWire a = new CoreWire(t, 3, 1), b = new CoreWire(t, 2, 1), c = new CoreWire(t, 3, 1), out = new CoreWire(t, 8, 1); a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO); b.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO); c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); - new UnidirectionalMerger(t, out.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); + new CoreUnidirectionalMerger(t, out.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); t.executeAll(); @@ -93,10 +93,10 @@ class ComponentTest @Test void fusionTest1() { - Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), out = new Wire(t, 8, 1); - Wire.fuse(a, out, 0, 0, a.width); - Wire.fuse(b, out, 0, a.width, b.width); - Wire.fuse(c, out, 0, a.width + b.width, c.width); + CoreWire a = new CoreWire(t, 3, 1), b = new CoreWire(t, 2, 1), c = new CoreWire(t, 3, 1), out = new CoreWire(t, 8, 1); + CoreWire.fuse(a, out, 0, 0, a.width); + CoreWire.fuse(b, out, 0, a.width, b.width); + CoreWire.fuse(c, out, 0, a.width + b.width, c.width); ReadWriteEnd rA = a.createReadWriteEnd(); rA.feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO); ReadWriteEnd rB = b.createReadWriteEnd(); @@ -123,8 +123,8 @@ class ComponentTest @Test void fusionTest2() { - Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 1); - Wire.fuse(a, b); + CoreWire a = new CoreWire(t, 3, 1), b = new CoreWire(t, 3, 1); + CoreWire.fuse(a, b); ReadWriteEnd rw = a.createReadWriteEnd(); t.executeAll(); assertBitArrayEquals(b.getValues(), Bit.U, Bit.U, Bit.U); @@ -137,10 +137,10 @@ class ComponentTest @Test void fusionTest3() { - Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 1); + CoreWire a = new CoreWire(t, 3, 1), b = new CoreWire(t, 3, 1); a.createReadWriteEnd().feedSignals(Bit.Z, Bit.U, Bit.X); t.executeAll(); - Wire.fuse(a, b); + CoreWire.fuse(a, b); t.executeAll(); assertBitArrayEquals(b.getValues(), Bit.Z, Bit.U, Bit.X); } @@ -148,11 +148,11 @@ class ComponentTest @Test void fusionTest4() { - Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 1); + CoreWire a = new CoreWire(t, 3, 1), b = new CoreWire(t, 3, 1); a.createReadWriteEnd(); t.executeAll(); - Wire.fuse(a, b); + CoreWire.fuse(a, b); t.executeAll(); assertBitArrayEquals(b.getValues(), Bit.U, Bit.U, Bit.U); } @@ -172,10 +172,10 @@ class ComponentTest @Test void triStateBufferTest() { - Wire a = new Wire(t, 1, 1), b = new Wire(t, 1, 1), en = new Wire(t, 1, 1), notEn = new Wire(t, 1, 1); - new NotGate(t, 1, en.createReadOnlyEnd(), notEn.createReadWriteEnd()); - new TriStateBuffer(t, 1, a.createReadOnlyEnd(), b.createReadWriteEnd(), en.createReadOnlyEnd()); - new TriStateBuffer(t, 1, b.createReadOnlyEnd(), a.createReadWriteEnd(), notEn.createReadOnlyEnd()); + CoreWire a = new CoreWire(t, 1, 1), b = new CoreWire(t, 1, 1), en = new CoreWire(t, 1, 1), notEn = new CoreWire(t, 1, 1); + new CoreNotGate(t, 1, en.createReadOnlyEnd(), notEn.createReadWriteEnd()); + new CoreTriStateBuffer(t, 1, a.createReadOnlyEnd(), b.createReadWriteEnd(), en.createReadOnlyEnd()); + new CoreTriStateBuffer(t, 1, b.createReadOnlyEnd(), a.createReadWriteEnd(), notEn.createReadOnlyEnd()); ReadWriteEnd enI = en.createReadWriteEnd(), aI = a.createReadWriteEnd(), bI = b.createReadWriteEnd(); enI.feedSignals(Bit.ONE); @@ -205,14 +205,14 @@ class ComponentTest @Test void muxTest() { - Wire a = new Wire(t, 4, 3), b = new Wire(t, 4, 6), c = new Wire(t, 4, 4), select = new Wire(t, 2, 5), out = new Wire(t, 4, 1); + CoreWire a = new CoreWire(t, 4, 3), b = new CoreWire(t, 4, 6), c = new CoreWire(t, 4, 4), select = new CoreWire(t, 2, 5), out = new CoreWire(t, 4, 1); ReadWriteEnd selectIn = select.createReadWriteEnd(); selectIn.feedSignals(Bit.ZERO, Bit.ZERO); a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); c.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); - new Mux(t, 1, out.createReadWriteEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), + new CoreMux(t, 1, out.createReadWriteEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); t.executeAll(); @@ -232,13 +232,13 @@ class ComponentTest @Test void demuxTest() { - Wire a = new Wire(t, 4, 3), b = new Wire(t, 4, 6), c = new Wire(t, 4, 4), select = new Wire(t, 2, 5), in = new Wire(t, 4, 1); + CoreWire a = new CoreWire(t, 4, 3), b = new CoreWire(t, 4, 6), c = new CoreWire(t, 4, 4), select = new CoreWire(t, 2, 5), in = new CoreWire(t, 4, 1); ReadWriteEnd selectIn = select.createReadWriteEnd(); selectIn.feedSignals(Bit.ZERO, Bit.ZERO); in.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO); - new Demux(t, 1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(), + new CoreDemux(t, 1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(), c.createReadWriteEnd()); t.executeAll(); @@ -264,8 +264,8 @@ class ComponentTest @Test void andTest() { - Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1); - new AndGate(t, 1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); + CoreWire a = new CoreWire(t, 4, 1), b = new CoreWire(t, 4, 3), c = new CoreWire(t, 4, 1); + new CoreAndGate(t, 1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); @@ -277,8 +277,8 @@ class ComponentTest @Test void orTest() { - Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1); - new OrGate(t, 1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); + CoreWire a = new CoreWire(t, 4, 1), b = new CoreWire(t, 4, 3), c = new CoreWire(t, 4, 1); + new CoreOrGate(t, 1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd()); a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); @@ -290,8 +290,8 @@ class ComponentTest @Test void nandTest() { - Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1), d = new Wire(t, 4, 1); - new NandGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); + CoreWire a = new CoreWire(t, 4, 1), b = new CoreWire(t, 4, 3), c = new CoreWire(t, 4, 1), d = new CoreWire(t, 4, 1); + new CoreNandGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); @@ -304,8 +304,8 @@ class ComponentTest @Test void norTest() { - Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1), d = new Wire(t, 4, 1); - new NorGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); + CoreWire a = new CoreWire(t, 4, 1), b = new CoreWire(t, 4, 3), c = new CoreWire(t, 4, 1), d = new CoreWire(t, 4, 1); + new CoreNorGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE); c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO); @@ -318,8 +318,8 @@ class ComponentTest @Test void xorTest() { - Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 2), c = new Wire(t, 3, 1), d = new Wire(t, 3, 1); - new XorGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); + CoreWire a = new CoreWire(t, 3, 1), b = new CoreWire(t, 3, 2), c = new CoreWire(t, 3, 1), d = new CoreWire(t, 3, 1); + new CoreXorGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd()); a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE); b.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE); @@ -332,8 +332,8 @@ class ComponentTest @Test void notTest() { - Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 2); - new NotGate(t, 1, a.createReadOnlyEnd(), b.createReadWriteEnd()); + CoreWire a = new CoreWire(t, 3, 1), b = new CoreWire(t, 3, 2); + new CoreNotGate(t, 1, a.createReadOnlyEnd(), b.createReadWriteEnd()); a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE); t.executeAll(); @@ -344,13 +344,13 @@ class ComponentTest @Test void rsLatchCircuitTest() { - Wire r = new Wire(t, 1, 1), s = new Wire(t, 1, 1), t1 = new Wire(t, 1, 15), t2 = new Wire(t, 1, 1), q = new Wire(t, 1, 1), - nq = new Wire(t, 1, 1); + CoreWire r = new CoreWire(t, 1, 1), s = new CoreWire(t, 1, 1), t1 = new CoreWire(t, 1, 15), t2 = new CoreWire(t, 1, 1), q = new CoreWire(t, 1, 1), + nq = new CoreWire(t, 1, 1); - new OrGate(t, 1, t2.createReadWriteEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd()); - new OrGate(t, 1, t1.createReadWriteEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd()); - new NotGate(t, 1, t2.createReadOnlyEnd(), q.createReadWriteEnd()); - new NotGate(t, 1, t1.createReadOnlyEnd(), nq.createReadWriteEnd()); + new CoreOrGate(t, 1, t2.createReadWriteEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd()); + new CoreOrGate(t, 1, t1.createReadWriteEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd()); + new CoreNotGate(t, 1, t2.createReadOnlyEnd(), q.createReadWriteEnd()); + new CoreNotGate(t, 1, t1.createReadOnlyEnd(), nq.createReadWriteEnd()); ReadWriteEnd sIn = s.createReadWriteEnd(), rIn = r.createReadWriteEnd(); @@ -379,7 +379,7 @@ class ComponentTest @Test void numericValueTest() { - Wire a = new Wire(t, 4, 1); + CoreWire a = new CoreWire(t, 4, 1); a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ONE, Bit.ONE); t.executeAll(); @@ -429,7 +429,7 @@ class ComponentTest @Test void multipleInputs() { - Wire w = new Wire(t, 2, 1); + CoreWire w = new CoreWire(t, 2, 1); ReadWriteEnd wI1 = w.createReadWriteEnd(), wI2 = w.createReadWriteEnd(); wI1.feedSignals(Bit.ONE, Bit.Z); wI2.feedSignals(Bit.Z, Bit.X); diff --git a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/GUITest.java b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/GUITest.java index 86eb115d..a3689a30 100644 --- a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/GUITest.java +++ b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/GUITest.java @@ -15,12 +15,12 @@ import javax.swing.JFrame; import javax.swing.JPanel; import javax.swing.WindowConstants; -import net.mograsim.logic.core.components.ManualSwitch; -import net.mograsim.logic.core.components.gates.NotGate; -import net.mograsim.logic.core.components.gates.OrGate; +import net.mograsim.logic.core.components.CoreManualSwitch; +import net.mograsim.logic.core.components.gates.CoreNotGate; +import net.mograsim.logic.core.components.gates.CoreOrGate; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.timeline.Timeline.ExecutionResult; -import net.mograsim.logic.core.wires.Wire; +import net.mograsim.logic.core.wires.CoreWire; public class GUITest extends JPanel { @@ -33,22 +33,22 @@ public class GUITest extends JPanel private Timeline t = new Timeline(11); - Wire r = new Wire(t, 1, WIRE_DELAY); - Wire s = new Wire(t, 1, WIRE_DELAY); - Wire t1 = new Wire(t, 1, WIRE_DELAY); - Wire t2 = new Wire(t, 1, WIRE_DELAY); - Wire q = new Wire(t, 1, WIRE_DELAY); - Wire nq = new Wire(t, 1, WIRE_DELAY); + CoreWire r = new CoreWire(t, 1, WIRE_DELAY); + CoreWire s = new CoreWire(t, 1, WIRE_DELAY); + CoreWire t1 = new CoreWire(t, 1, WIRE_DELAY); + CoreWire t2 = new CoreWire(t, 1, WIRE_DELAY); + CoreWire q = new CoreWire(t, 1, WIRE_DELAY); + CoreWire nq = new CoreWire(t, 1, WIRE_DELAY); - ManualSwitch rIn = new ManualSwitch(t, r.createReadWriteEnd()); - ManualSwitch sIn = new ManualSwitch(t, s.createReadWriteEnd()); + CoreManualSwitch rIn = new CoreManualSwitch(t, r.createReadWriteEnd()); + CoreManualSwitch sIn = new CoreManualSwitch(t, s.createReadWriteEnd()); - OrGate or1 = new OrGate(t, OR_DELAY, t2.createReadWriteEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd()); - OrGate or2 = new OrGate(t, OR_DELAY, t1.createReadWriteEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd()); - NotGate not1 = new NotGate(t, NOT_DELAY, t2.createReadOnlyEnd(), q.createReadWriteEnd()); - NotGate not2 = new NotGate(t, NOT_DELAY, t1.createReadOnlyEnd(), nq.createReadWriteEnd()); + CoreOrGate or1 = new CoreOrGate(t, OR_DELAY, t2.createReadWriteEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd()); + CoreOrGate or2 = new CoreOrGate(t, OR_DELAY, t1.createReadWriteEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd()); + CoreNotGate not1 = new CoreNotGate(t, NOT_DELAY, t2.createReadOnlyEnd(), q.createReadWriteEnd()); + CoreNotGate not2 = new CoreNotGate(t, NOT_DELAY, t1.createReadOnlyEnd(), nq.createReadWriteEnd()); - Map switchMap = new HashMap<>(); + Map switchMap = new HashMap<>(); int height; int width; @@ -62,7 +62,7 @@ public class GUITest extends JPanel @Override public void mouseReleased(MouseEvent e) { - for (Entry dim : switchMap.entrySet()) + for (Entry dim : switchMap.entrySet()) { if (dim.getValue().contains(e.getPoint())) { @@ -75,7 +75,7 @@ public class GUITest extends JPanel @Override public void mousePressed(MouseEvent e) { - for (Entry dim : switchMap.entrySet()) + for (Entry dim : switchMap.entrySet()) { if (dim.getValue().contains(e.getPoint())) { @@ -185,7 +185,7 @@ public class GUITest extends JPanel g.drawString(s, x - (int) (w * anchorX), y + (int) (h * anchorY)); } - private void drawWire(Graphics g, Wire wa, String name, double x1, double y1, double x2, double y2) + private void drawWire(Graphics g, CoreWire wa, String name, double x1, double y1, double x2, double y2) { setTo(g, wa); g.drawLine(gX(x1), gY(y1), gX(x2), gY(y2)); @@ -207,7 +207,7 @@ public class GUITest extends JPanel } - private void drawSwitch(Graphics g, ManualSwitch ms, String text, double posX1, double posY1, double posX2, double posY2) + private void drawSwitch(Graphics g, CoreManualSwitch ms, String text, double posX1, double posY1, double posX2, double posY2) { int x1 = gX(posX1) - 5; int x2 = gX(posX2) + 5; @@ -232,7 +232,7 @@ public class GUITest extends JPanel g.setColor(Color.BLACK); } - private static void setTo(Graphics g, Wire wa) + private static void setTo(Graphics g, CoreWire wa) { switch (wa.getValue()) { diff --git a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/TestBitDisplay.java b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/TestCoreBitDisplay.java similarity index 78% rename from net.mograsim.logic.core/test/net/mograsim/logic/core/tests/TestBitDisplay.java rename to net.mograsim.logic.core/test/net/mograsim/logic/core/tests/TestCoreBitDisplay.java index 015e257f..2e5e5fd6 100644 --- a/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/TestBitDisplay.java +++ b/net.mograsim.logic.core/test/net/mograsim/logic/core/tests/TestCoreBitDisplay.java @@ -4,15 +4,15 @@ import static org.junit.jupiter.api.Assertions.assertArrayEquals; import java.util.function.LongConsumer; -import net.mograsim.logic.core.components.BitDisplay; +import net.mograsim.logic.core.components.CoreBitDisplay; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.Bit; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; -public final class TestBitDisplay extends BitDisplay +public final class TestCoreBitDisplay extends CoreBitDisplay { - public TestBitDisplay(Timeline timeline, ReadEnd in) + public TestCoreBitDisplay(Timeline timeline, ReadEnd in) { super(timeline, in); } diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIdff12.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIdff12.java index 03e26d44..f412554e 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIdff12.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIdff12.java @@ -9,8 +9,8 @@ import java.util.Map; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIdff4_finewe.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIdff4_finewe.java index 6c857b64..8781f1ac 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIdff4_finewe.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIdff4_finewe.java @@ -11,8 +11,8 @@ import java.util.Map; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIinc12.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIinc12.java index 744b326a..ca740768 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIinc12.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIinc12.java @@ -9,8 +9,8 @@ import java.util.Arrays; import java.util.Map; import net.mograsim.logic.core.types.Bit; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUInor12.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUInor12.java index 3ceb01cb..bb36801d 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUInor12.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUInor12.java @@ -9,8 +9,8 @@ import static net.mograsim.logic.core.types.Bit.ZERO; import java.util.Map; import net.mograsim.logic.core.types.Bit; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIram5_12.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIram5_12.java index f46b68d1..4a13c471 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIram5_12.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIram5_12.java @@ -13,8 +13,8 @@ import java.util.regex.Pattern; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIsel4_12.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIsel4_12.java index 17b70a5f..3b88d72a 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIsel4_12.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/GUIsel4_12.java @@ -10,8 +10,8 @@ import java.util.Map; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904RegCTInstrDecode.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904RegCTInstrDecode.java index 664893ba..4fff66bb 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904RegCTInstrDecode.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904RegCTInstrDecode.java @@ -9,8 +9,8 @@ import java.util.Map; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904ShiftInstrDecode.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904ShiftInstrDecode.java index 04dc9334..9f3865cc 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904ShiftInstrDecode.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904ShiftInstrDecode.java @@ -10,8 +10,8 @@ import java.util.Map; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910InstrPLA.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910InstrPLA.java index 960cc740..96831419 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910InstrPLA.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910InstrPLA.java @@ -8,8 +8,8 @@ import static net.mograsim.logic.core.types.Bit.ZERO; import java.util.Map; import net.mograsim.logic.core.types.Bit; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910RegCntr.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910RegCntr.java index 8451327e..964637d8 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910RegCntr.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910RegCntr.java @@ -9,8 +9,8 @@ import java.util.Map; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910SP.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910SP.java index cbd4251d..2be4d04b 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910SP.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/GUIAm2910SP.java @@ -9,8 +9,8 @@ import java.util.Map; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/machine/Am2900Machine.java b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/machine/Am2900Machine.java index f8abe443..3c6ca1c2 100644 --- a/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/machine/Am2900Machine.java +++ b/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/machine/Am2900Machine.java @@ -1,6 +1,6 @@ package net.mograsim.logic.model.am2900.machine; -import net.mograsim.logic.core.components.Clock; +import net.mograsim.logic.core.components.CoreClock; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.BitVector; import net.mograsim.logic.model.model.ViewModel; @@ -17,7 +17,7 @@ public class Am2900Machine implements Machine private Am2900MachineDefinition machineDefinition; private ViewModelModifiable viewModel; private Timeline timeline; - private Clock clock; + private CoreClock clock; public Am2900Machine(Am2900MachineDefinition am2900MachineDefinition) { @@ -57,7 +57,7 @@ public class Am2900Machine implements Machine } @Override - public Clock getClock() + public CoreClock getClock() { return clock; } diff --git a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2901/TestableAm2901Impl.java b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2901/TestableAm2901Impl.java index 43e01d43..45e9e044 100644 --- a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2901/TestableAm2901Impl.java +++ b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2901/TestableAm2901Impl.java @@ -1,7 +1,7 @@ package net.mograsim.logic.model.am2900.am2901; -import net.mograsim.logic.core.components.BitDisplay; -import net.mograsim.logic.core.components.ManualSwitch; +import net.mograsim.logic.core.components.CoreBitDisplay; +import net.mograsim.logic.core.components.CoreManualSwitch; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; import net.mograsim.logic.model.am2900.util.SwitchWithDisplay; @@ -13,14 +13,14 @@ import net.mograsim.logic.model.model.components.GUIComponent; public class TestableAm2901Impl implements TestableAm2901 { private GUIComponent am2901; - private ManualSwitch I8, I7, I6, I5, I4, I3, I2, I1, I0; - private ManualSwitch C; - private ManualSwitch Cn; - private ManualSwitch D1, D2, D3, D4; - private ManualSwitch A0, A1, A2, A3; - private ManualSwitch B0, B1, B2, B3; - private BitDisplay Y1, Y2, Y3, Y4; - private BitDisplay F_0, Cn_4, OVR, F3; + private CoreManualSwitch I8, I7, I6, I5, I4, I3, I2, I1, I0; + private CoreManualSwitch C; + private CoreManualSwitch Cn; + private CoreManualSwitch D1, D2, D3, D4; + private CoreManualSwitch A0, A1, A2, A3; + private CoreManualSwitch B0, B1, B2, B3; + private CoreBitDisplay Y1, Y2, Y3, Y4; + private CoreBitDisplay F_0, Cn_4, OVR, F3; private SwitchWithDisplay RAMn, RAMn_3, Qn, Qn_3; private final TestEnvironmentHelper testHelper = new TestEnvironmentHelper(this, "GUIAm2901"); diff --git a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2904/TestableAm2904Impl.java b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2904/TestableAm2904Impl.java index cebd986b..6d926384 100644 --- a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2904/TestableAm2904Impl.java +++ b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2904/TestableAm2904Impl.java @@ -1,7 +1,7 @@ package net.mograsim.logic.model.am2900.am2904; -import net.mograsim.logic.core.components.BitDisplay; -import net.mograsim.logic.core.components.ManualSwitch; +import net.mograsim.logic.core.components.CoreBitDisplay; +import net.mograsim.logic.core.components.CoreManualSwitch; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; import net.mograsim.logic.model.am2900.util.SwitchWithDisplay; @@ -13,16 +13,16 @@ public class TestableAm2904Impl implements TestableAm2904 { private GUIComponent am2904; - private ManualSwitch I; - private ManualSwitch C; - private ManualSwitch Cx; - private ManualSwitch IC, IN, IOVR, IZ; - private ManualSwitch _CEM, _CEmu; - private ManualSwitch _EC, _EN, _EOVR, _EZ; - private ManualSwitch _OECT, _OEY; - private ManualSwitch _SE; - private BitDisplay C0; - private BitDisplay CT; + private CoreManualSwitch I; + private CoreManualSwitch C; + private CoreManualSwitch Cx; + private CoreManualSwitch IC, IN, IOVR, IZ; + private CoreManualSwitch _CEM, _CEmu; + private CoreManualSwitch _EC, _EN, _EOVR, _EZ; + private CoreManualSwitch _OECT, _OEY; + private CoreManualSwitch _SE; + private CoreBitDisplay C0; + private CoreBitDisplay CT; private SwitchWithDisplay SIO0, SIOn, QIO0, QIOn; private SwitchWithDisplay YC, YN, YOVR, YZ; diff --git a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2910/TestableAm2910Impl.java b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2910/TestableAm2910Impl.java index 436fe838..a7d25252 100644 --- a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2910/TestableAm2910Impl.java +++ b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/am2910/TestableAm2910Impl.java @@ -1,7 +1,7 @@ package net.mograsim.logic.model.am2900.am2910; -import net.mograsim.logic.core.components.BitDisplay; -import net.mograsim.logic.core.components.ManualSwitch; +import net.mograsim.logic.core.components.CoreBitDisplay; +import net.mograsim.logic.core.components.CoreManualSwitch; import net.mograsim.logic.core.types.BitVector; import net.mograsim.logic.model.am2900.util.TestEnvironmentHelper; import net.mograsim.logic.model.am2900.util.TestEnvironmentHelper.DebugState; @@ -11,17 +11,17 @@ public class TestableAm2910Impl implements TestableAm2910 { private GUIComponent am2901; - private ManualSwitch I; - private ManualSwitch C; - private ManualSwitch CI; - private ManualSwitch D; - private ManualSwitch _CC; - private ManualSwitch _CCEN; - private ManualSwitch _RLD; - private ManualSwitch _OE; - private BitDisplay _FULL; - private BitDisplay Y; - private BitDisplay _PL, _MAP, _VECT; + private CoreManualSwitch I; + private CoreManualSwitch C; + private CoreManualSwitch CI; + private CoreManualSwitch D; + private CoreManualSwitch _CC; + private CoreManualSwitch _CCEN; + private CoreManualSwitch _RLD; + private CoreManualSwitch _OE; + private CoreBitDisplay _FULL; + private CoreBitDisplay Y; + private CoreBitDisplay _PL, _MAP, _VECT; private final TestEnvironmentHelper testHelper = new TestEnvironmentHelper(this, "GUIAm2910"); diff --git a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/util/SwitchWithDisplay.java b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/util/SwitchWithDisplay.java index 2591e3a5..c5ee27b8 100644 --- a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/util/SwitchWithDisplay.java +++ b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/util/SwitchWithDisplay.java @@ -1,7 +1,7 @@ package net.mograsim.logic.model.am2900.util; -import net.mograsim.logic.core.components.BitDisplay; -import net.mograsim.logic.core.components.ManualSwitch; +import net.mograsim.logic.core.components.CoreBitDisplay; +import net.mograsim.logic.core.components.CoreManualSwitch; import net.mograsim.logic.core.types.BitVector; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.atomic.GUIBitDisplay; @@ -43,12 +43,12 @@ public class SwitchWithDisplay return pin; } - public final BitDisplay getBitDisplay() + public final CoreBitDisplay getBitDisplay() { return guiBitDisplay.getBitDisplay(); } - public final ManualSwitch getManualSwitch() + public final CoreManualSwitch getManualSwitch() { return guiManualSwitch.getManualSwitch(); } diff --git a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/util/TestEnvironmentHelper.java b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/util/TestEnvironmentHelper.java index 9fb7bcd9..9707b9ae 100644 --- a/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/util/TestEnvironmentHelper.java +++ b/net.mograsim.logic.model.am2900/test/net/mograsim/logic/model/am2900/util/TestEnvironmentHelper.java @@ -12,8 +12,8 @@ import java.util.Queue; import java.util.Set; import java.util.TreeSet; -import net.mograsim.logic.core.components.BitDisplay; -import net.mograsim.logic.core.components.ManualSwitch; +import net.mograsim.logic.core.components.CoreBitDisplay; +import net.mograsim.logic.core.components.CoreManualSwitch; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.model.LogicUIStandaloneGUI; import net.mograsim.logic.model.am2900.Am2900Loader; @@ -111,12 +111,12 @@ public class TestEnvironmentHelper { Field f = testEnvClass.getDeclaredField(javaIdentId); Class type = f.getType(); - if (ManualSwitch.class.isAssignableFrom(type)) + if (CoreManualSwitch.class.isAssignableFrom(type)) { GUIManualSwitch gms = new GUIManualSwitch(viewModel, p.logicWidth); modellingTool.connect(p, gms.getOutputPin()); idSwitchMap.put(p.name, gms); - } else if (BitDisplay.class.isAssignableFrom(type)) + } else if (CoreBitDisplay.class.isAssignableFrom(type)) { GUIBitDisplay gbd = new GUIBitDisplay(viewModel, p.logicWidth); modellingTool.connect(p, gbd.getInputPin()); diff --git a/net.mograsim.logic.model.editor/src/net/mograsim/logic/model/editor/handles/WirePointHandle.java b/net.mograsim.logic.model.editor/src/net/mograsim/logic/model/editor/handles/WirePointHandle.java index 4c0b9a31..b7cc23e9 100644 --- a/net.mograsim.logic.model.editor/src/net/mograsim/logic/model/editor/handles/WirePointHandle.java +++ b/net.mograsim.logic.model.editor/src/net/mograsim/logic/model/editor/handles/WirePointHandle.java @@ -5,7 +5,7 @@ import org.eclipse.swt.widgets.Display; import net.haspamelodica.swt.helper.gcs.GeneralGC; import net.haspamelodica.swt.helper.swtobjectwrappers.Point; -import net.mograsim.logic.core.wires.Wire; +import net.mograsim.logic.core.wires.CoreWire; import net.mograsim.logic.model.model.wires.GUIWire; public class WirePointHandle extends Handle @@ -76,7 +76,7 @@ public class WirePointHandle extends Handle } /** - * Sets the index of the {@link Point} within the parent {@link Wire}s path that is controlled by this handle + * Sets the index of the {@link Point} within the parent {@link CoreWire}s path that is controlled by this handle * * @param index Index of the Point in the Wires path. * @throws IndexOutOfBoundsException diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIAndGate.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIAndGate.java index f9fd506b..d2f656f8 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIAndGate.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIAndGate.java @@ -1,6 +1,6 @@ package net.mograsim.logic.model.model.components.atomic; -import net.mograsim.logic.core.components.gates.AndGate; +import net.mograsim.logic.core.components.gates.CoreAndGate; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.modeladapter.ViewLogicModelAdapter; import net.mograsim.logic.model.modeladapter.componentadapters.SimpleGateAdapter; @@ -21,7 +21,7 @@ public class GUIAndGate extends SimpleRectangularGUIGate static { - ViewLogicModelAdapter.addComponentAdapter(new SimpleGateAdapter<>(GUIAndGate.class, AndGate::new)); + ViewLogicModelAdapter.addComponentAdapter(new SimpleGateAdapter<>(GUIAndGate.class, CoreAndGate::new)); IndirectGUIComponentCreator.setComponentSupplier(GUIAndGate.class.getCanonicalName(), (m, p, n) -> new GUIAndGate(m, p.getAsInt(), n)); } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIBitDisplay.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIBitDisplay.java index 8d96d0a9..ac92ecba 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIBitDisplay.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIBitDisplay.java @@ -7,7 +7,7 @@ import net.haspamelodica.swt.helper.swtobjectwrappers.Font; import net.haspamelodica.swt.helper.swtobjectwrappers.Point; import net.haspamelodica.swt.helper.swtobjectwrappers.Rectangle; import net.mograsim.logic.core.LogicObserver; -import net.mograsim.logic.core.components.BitDisplay; +import net.mograsim.logic.core.components.CoreBitDisplay; import net.mograsim.logic.core.types.BitVectorFormatter; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.GUIComponent; @@ -29,7 +29,7 @@ public class GUIBitDisplay extends GUIComponent private final Pin inputPin; private final LogicObserver logicObs; - private BitDisplay bitDisplay; + private CoreBitDisplay bitDisplay; public GUIBitDisplay(ViewModelModifiable model, int logicWidth) { @@ -66,7 +66,7 @@ public class GUIBitDisplay extends GUIComponent gc.setFont(oldFont); } - public void setLogicModelBinding(BitDisplay bitDisplay) + public void setLogicModelBinding(CoreBitDisplay bitDisplay) { if (this.bitDisplay != null) this.bitDisplay.deregisterObserver(logicObs); @@ -80,7 +80,7 @@ public class GUIBitDisplay extends GUIComponent return bitDisplay != null; } - public BitDisplay getBitDisplay() + public CoreBitDisplay getBitDisplay() { return bitDisplay; } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIClock.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIClock.java index ffc11151..5d314cc1 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIClock.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIClock.java @@ -9,7 +9,7 @@ import net.haspamelodica.swt.helper.swtobjectwrappers.Font; import net.haspamelodica.swt.helper.swtobjectwrappers.Point; import net.haspamelodica.swt.helper.swtobjectwrappers.Rectangle; import net.mograsim.logic.core.LogicObserver; -import net.mograsim.logic.core.components.Clock; +import net.mograsim.logic.core.components.CoreClock; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.GUIComponent; import net.mograsim.logic.model.model.components.Orientation; @@ -34,7 +34,7 @@ public class GUIClock extends GUIComponent private final LogicObserver logicObs; private GUIClockParams params; private OrientationCalculator oc; - private Clock clock; + private CoreClock clock; public GUIClock(ViewModelModifiable model, GUIClockParams params) { @@ -73,7 +73,7 @@ public class GUIClock extends GUIComponent gc.setFont(oldFont); } - public void setLogicModelBinding(Clock clock) + public void setLogicModelBinding(CoreClock clock) { if (this.clock != null) this.clock.deregisterObserver(logicObs); @@ -113,7 +113,7 @@ public class GUIClock extends GUIComponent } } - public Clock getClock() + public CoreClock getClock() { return clock; } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIManualSwitch.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIManualSwitch.java index fce4fff9..48bff90f 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIManualSwitch.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIManualSwitch.java @@ -7,7 +7,7 @@ import net.haspamelodica.swt.helper.swtobjectwrappers.Font; import net.haspamelodica.swt.helper.swtobjectwrappers.Point; import net.haspamelodica.swt.helper.swtobjectwrappers.Rectangle; import net.mograsim.logic.core.LogicObserver; -import net.mograsim.logic.core.components.ManualSwitch; +import net.mograsim.logic.core.components.CoreManualSwitch; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; import net.mograsim.logic.core.types.BitVectorFormatter; @@ -32,7 +32,7 @@ public class GUIManualSwitch extends GUIComponent private final Pin outputPin; private final LogicObserver logicObs; - private ManualSwitch logicSwitch; + private CoreManualSwitch logicSwitch; public GUIManualSwitch(ViewModelModifiable model, int logicWidth) { @@ -92,7 +92,7 @@ public class GUIManualSwitch extends GUIComponent } } - public void setLogicModelBinding(ManualSwitch logicSwitch) + public void setLogicModelBinding(CoreManualSwitch logicSwitch) { if (this.logicSwitch != null) this.logicSwitch.deregisterObserver(logicObs); @@ -152,7 +152,7 @@ public class GUIManualSwitch extends GUIComponent return true; } - public ManualSwitch getManualSwitch() + public CoreManualSwitch getManualSwitch() { return logicSwitch; } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIMerger.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIMerger.java index d7ec677a..804f871d 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIMerger.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIMerger.java @@ -5,7 +5,7 @@ import org.eclipse.swt.SWT; import net.haspamelodica.swt.helper.gcs.GeneralGC; import net.haspamelodica.swt.helper.swtobjectwrappers.Rectangle; import net.mograsim.logic.core.types.BitVectorFormatter; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.GUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUINandGate.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUINandGate.java index 0a8b04da..ddad7f82 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUINandGate.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUINandGate.java @@ -1,6 +1,6 @@ package net.mograsim.logic.model.model.components.atomic; -import net.mograsim.logic.core.components.gates.NandGate; +import net.mograsim.logic.core.components.gates.CoreNandGate; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.modeladapter.ViewLogicModelAdapter; import net.mograsim.logic.model.modeladapter.componentadapters.SimpleGateAdapter; @@ -21,7 +21,7 @@ public class GUINandGate extends SimpleRectangularGUIGate static { - ViewLogicModelAdapter.addComponentAdapter(new SimpleGateAdapter<>(GUINandGate.class, NandGate::new)); + ViewLogicModelAdapter.addComponentAdapter(new SimpleGateAdapter<>(GUINandGate.class, CoreNandGate::new)); IndirectGUIComponentCreator.setComponentSupplier(GUINandGate.class.getCanonicalName(), (m, p, n) -> new GUINandGate(m, p.getAsInt(), n)); } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUINotGate.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUINotGate.java index f9fcb4f6..c6001d29 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUINotGate.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUINotGate.java @@ -1,6 +1,6 @@ package net.mograsim.logic.model.model.components.atomic; -import net.mograsim.logic.core.components.gates.NotGate; +import net.mograsim.logic.core.components.gates.CoreNotGate; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.modeladapter.ViewLogicModelAdapter; import net.mograsim.logic.model.modeladapter.componentadapters.SimpleGateAdapter; @@ -21,7 +21,7 @@ public class GUINotGate extends SimpleRectangularGUIGate static { - ViewLogicModelAdapter.addComponentAdapter(new SimpleGateAdapter<>(GUINotGate.class, (t, p, o, i) -> new NotGate(t, p, i[0], o))); + ViewLogicModelAdapter.addComponentAdapter(new SimpleGateAdapter<>(GUINotGate.class, (t, p, o, i) -> new CoreNotGate(t, p, i[0], o))); IndirectGUIComponentCreator.setComponentSupplier(GUINotGate.class.getCanonicalName(), (m, p, n) -> new GUINotGate(m, p.getAsInt(), n)); } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIOrGate.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIOrGate.java index f1bd1ccc..6a6ba0f0 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIOrGate.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUIOrGate.java @@ -1,6 +1,6 @@ package net.mograsim.logic.model.model.components.atomic; -import net.mograsim.logic.core.components.gates.OrGate; +import net.mograsim.logic.core.components.gates.CoreOrGate; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.modeladapter.ViewLogicModelAdapter; import net.mograsim.logic.model.modeladapter.componentadapters.SimpleGateAdapter; @@ -21,7 +21,7 @@ public class GUIOrGate extends SimpleRectangularGUIGate static { - ViewLogicModelAdapter.addComponentAdapter(new SimpleGateAdapter<>(GUIOrGate.class, OrGate::new)); + ViewLogicModelAdapter.addComponentAdapter(new SimpleGateAdapter<>(GUIOrGate.class, CoreOrGate::new)); IndirectGUIComponentCreator.setComponentSupplier(GUIOrGate.class.getCanonicalName(), (m, p, n) -> new GUIOrGate(m, p.getAsInt(), n)); } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUISplitter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUISplitter.java index 43b744e4..4821c919 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUISplitter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/GUISplitter.java @@ -5,7 +5,7 @@ import org.eclipse.swt.SWT; import net.haspamelodica.swt.helper.gcs.GeneralGC; import net.haspamelodica.swt.helper.swtobjectwrappers.Rectangle; import net.mograsim.logic.core.types.BitVectorFormatter; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.GUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/SimpleRectangularHardcodedGUIComponent.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/SimpleRectangularHardcodedGUIComponent.java index b79b2e95..431240d7 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/SimpleRectangularHardcodedGUIComponent.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/SimpleRectangularHardcodedGUIComponent.java @@ -5,8 +5,8 @@ import java.util.concurrent.atomic.AtomicReference; import net.haspamelodica.swt.helper.gcs.GeneralGC; import net.haspamelodica.swt.helper.swtobjectwrappers.Rectangle; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.GUIComponent; import net.mograsim.logic.model.model.wires.Pin; diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/GUIWire.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/GUIWire.java index 870be5bc..e4b60105 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/GUIWire.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/GUIWire.java @@ -13,8 +13,8 @@ import net.haspamelodica.swt.helper.swtobjectwrappers.Rectangle; import net.mograsim.logic.core.LogicObserver; import net.mograsim.logic.core.types.BitVector; import net.mograsim.logic.core.types.BitVectorFormatter; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.preferences.ColorDefinition; import net.mograsim.preferences.ColorManager; @@ -492,7 +492,7 @@ public class GUIWire } /** - * If this {@link GUIWire} has a logic model binding, delegates to {@link Wire#forceValues(BitVector)} for the {@link Wire} + * If this {@link GUIWire} has a logic model binding, delegates to {@link CoreWire#forceValues(BitVector)} for the {@link CoreWire} * corresponding to this {@link GUIWire}. * * @author Daniel Kirschten diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/WireCrossPoint.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/WireCrossPoint.java index 7d31801a..d8863c21 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/WireCrossPoint.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/model/wires/WireCrossPoint.java @@ -4,7 +4,7 @@ import net.haspamelodica.swt.helper.gcs.GeneralGC; import net.haspamelodica.swt.helper.swtobjectwrappers.Rectangle; import net.mograsim.logic.core.LogicObserver; import net.mograsim.logic.core.types.BitVectorFormatter; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.logic.model.model.ViewModelModifiable; import net.mograsim.logic.model.model.components.GUIComponent; import net.mograsim.logic.model.serializing.IdentifyParams; diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/ViewLogicModelAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/ViewLogicModelAdapter.java index 6e722a0c..8c337cd2 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/ViewLogicModelAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/ViewLogicModelAdapter.java @@ -11,8 +11,8 @@ import java.util.function.Function; import java.util.stream.Collectors; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.logic.model.model.ViewModel; import net.mograsim.logic.model.model.components.GUIComponent; import net.mograsim.logic.model.model.components.submodels.SubmodelComponent; @@ -41,11 +41,11 @@ public class ViewLogicModelAdapter return timeline; } - private static void convert(ViewModel viewModel, LogicModelParameters params, Timeline timeline, Map externalWires) + private static void convert(ViewModel viewModel, LogicModelParameters params, Timeline timeline, Map externalWires) { - Map logicWiresPerPin = convertWires(getAllPins(viewModel), viewModel.getWiresByName().values(), externalWires, params, + Map logicWiresPerPin = convertWires(getAllPins(viewModel), viewModel.getWiresByName().values(), externalWires, params, timeline); - Map logicWiresPerPinUnmodifiable = Collections.unmodifiableMap(logicWiresPerPin); + Map logicWiresPerPinUnmodifiable = Collections.unmodifiableMap(logicWiresPerPin); for (GUIComponent guiComp : viewModel.getComponentsByName().values()) { @@ -53,7 +53,7 @@ public class ViewLogicModelAdapter { SubmodelComponent guiCompCasted = (SubmodelComponent) guiComp; Map supermodelPins = guiCompCasted.getSupermodelPins(); - Map externalWiresForSubmodel = supermodelPins.entrySet().stream() + Map externalWiresForSubmodel = supermodelPins.entrySet().stream() .collect(Collectors.toMap(e -> guiCompCasted.getSubmodelPin(e.getKey()), e -> logicWiresPerPin.get(e.getValue()))); convert(guiCompCasted.submodel, params, timeline, externalWiresForSubmodel); } else if (guiComp instanceof WireCrossPoint) @@ -71,45 +71,45 @@ public class ViewLogicModelAdapter .collect(Collectors.toSet()); } - private static Map convertWires(Set allPins, Collection wires, Map externalWires, + private static Map convertWires(Set allPins, Collection wires, Map externalWires, LogicModelParameters params, Timeline timeline) { Map> connectedPinGroups = getConnectedPinGroups(allPins, wires); - Map logicWiresPerPin = createLogicWires(params, timeline, connectedPinGroups, externalWires); + Map logicWiresPerPin = createLogicWires(params, timeline, connectedPinGroups, externalWires); setGUIWiresLogicModelBinding(wires, logicWiresPerPin); return logicWiresPerPin; } - private static Map createLogicWires(LogicModelParameters params, Timeline timeline, Map> connectedPinGroups, - Map externalWires) + private static Map createLogicWires(LogicModelParameters params, Timeline timeline, Map> connectedPinGroups, + Map externalWires) { - Map logicWiresPerPin = new HashMap<>(); - Map, Wire> logicWiresPerPinGroup = new HashMap<>(); + Map logicWiresPerPin = new HashMap<>(); + Map, CoreWire> logicWiresPerPinGroup = new HashMap<>(); for (Entry> e : connectedPinGroups.entrySet()) logicWiresPerPin.put(e.getKey(), logicWiresPerPinGroup.computeIfAbsent(e.getValue(), set -> { - Wire externalWire = null; + CoreWire externalWire = null; for (Pin p : set) { - Wire externalWireCandidate = externalWires.get(p); + CoreWire externalWireCandidate = externalWires.get(p); if (externalWireCandidate != null) if (externalWire == null) externalWire = externalWireCandidate; else if (externalWire.width == externalWireCandidate.width) - Wire.fuse(externalWire, externalWireCandidate); + CoreWire.fuse(externalWire, externalWireCandidate); else throw new IllegalArgumentException( "Two pins to external wires with different logicWidths can't be connected directly"); } - return externalWire == null ? new Wire(timeline, e.getKey().logicWidth, params.wireTravelTime) : externalWire; + return externalWire == null ? new CoreWire(timeline, e.getKey().logicWidth, params.wireTravelTime) : externalWire; })); return logicWiresPerPin; } - private static void setGUIWiresLogicModelBinding(Collection wires, Map logicWiresPerPin) + private static void setGUIWiresLogicModelBinding(Collection wires, Map logicWiresPerPin) { - Map guiWireSharedReadEnd = logicWiresPerPin.values().stream().distinct() - .collect(Collectors.toMap(Function.identity(), Wire::createReadOnlyEnd)); + Map guiWireSharedReadEnd = logicWiresPerPin.values().stream().distinct() + .collect(Collectors.toMap(Function.identity(), CoreWire::createReadOnlyEnd)); for (GUIWire guiWire : wires) guiWire.setLogicModelBinding(guiWireSharedReadEnd.get(logicWiresPerPin.get(guiWire.getPin1()))); } @@ -144,7 +144,7 @@ public class ViewLogicModelAdapter @SuppressWarnings("unchecked") private static void createAndLinkComponent(Timeline timeline, LogicModelParameters params, - GUIComponent guiComponent, Map logicWiresPerPin) + GUIComponent guiComponent, Map logicWiresPerPin) { Class cls = guiComponent.getClass(); ComponentAdapter adapter = null; diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/BitDisplayAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/BitDisplayAdapter.java index 7e0a063b..2303679b 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/BitDisplayAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/BitDisplayAdapter.java @@ -2,10 +2,10 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; -import net.mograsim.logic.core.components.BitDisplay; +import net.mograsim.logic.core.components.CoreBitDisplay; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.logic.model.model.components.atomic.GUIBitDisplay; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -20,10 +20,10 @@ public class BitDisplayAdapter implements ComponentAdapter @Override public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, GUIBitDisplay guiComponent, - Map logicWiresPerPin) + Map logicWiresPerPin) { ReadEnd end = logicWiresPerPin.get(guiComponent.getInputPin()).createReadOnlyEnd(); - BitDisplay bitDisplay = new BitDisplay(timeline, end); + CoreBitDisplay bitDisplay = new CoreBitDisplay(timeline, end); guiComponent.setLogicModelBinding(bitDisplay); } } \ No newline at end of file diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ClockAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ClockAdapter.java index 55d3edba..3066d35c 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ClockAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ClockAdapter.java @@ -2,10 +2,10 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; -import net.mograsim.logic.core.components.Clock; +import net.mograsim.logic.core.components.CoreClock; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.components.atomic.GUIClock; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -20,10 +20,10 @@ public class ClockAdapter implements ComponentAdapter } @Override - public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, GUIClock guiClock, Map logicWiresPerPin) + public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, GUIClock guiClock, Map logicWiresPerPin) { ReadWriteEnd out = logicWiresPerPin.get(guiClock.getOutputPin()).createReadWriteEnd(); - Clock c = new Clock(timeline, out, guiClock.getDelta()); + CoreClock c = new CoreClock(timeline, out, guiClock.getDelta()); guiClock.setLogicModelBinding(c); } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ComponentAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ComponentAdapter.java index b7780b3c..5ebe01b2 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ComponentAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ComponentAdapter.java @@ -3,7 +3,7 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; +import net.mograsim.logic.core.wires.CoreWire; import net.mograsim.logic.model.model.components.GUIComponent; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -12,5 +12,5 @@ public interface ComponentAdapter { public Class getSupportedClass(); - public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, G guiComponent, Map logicWiresPerPin); + public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, G guiComponent, Map logicWiresPerPin); } \ No newline at end of file diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/FixedOutputAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/FixedOutputAdapter.java index 03fa400b..618bbfc5 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/FixedOutputAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/FixedOutputAdapter.java @@ -3,7 +3,7 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; +import net.mograsim.logic.core.wires.CoreWire; import net.mograsim.logic.model.model.components.atomic.GUIFixedOutput; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -18,7 +18,7 @@ public class FixedOutputAdapter implements ComponentAdapter @Override public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, GUIFixedOutput guiComponent, - Map logicWiresPerPin) + Map logicWiresPerPin) { logicWiresPerPin.get(guiComponent.getPin("out")).createReadWriteEnd().feedSignals(guiComponent.bits); } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ManualSwitchAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ManualSwitchAdapter.java index 518db91d..0350ad6b 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ManualSwitchAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/ManualSwitchAdapter.java @@ -2,10 +2,10 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; -import net.mograsim.logic.core.components.ManualSwitch; +import net.mograsim.logic.core.components.CoreManualSwitch; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.components.atomic.GUIManualSwitch; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -20,10 +20,10 @@ public class ManualSwitchAdapter implements ComponentAdapter @Override public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, GUIManualSwitch guiComponent, - Map logicWiresPerPin) + Map logicWiresPerPin) { ReadWriteEnd end = logicWiresPerPin.get(guiComponent.getOutputPin()).createReadWriteEnd(); - ManualSwitch manualSwitch = new ManualSwitch(timeline, end); + CoreManualSwitch manualSwitch = new CoreManualSwitch(timeline, end); guiComponent.setLogicModelBinding(manualSwitch); } } \ No newline at end of file diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/MergerAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/MergerAdapter.java index cb3057e5..fcbd615c 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/MergerAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/MergerAdapter.java @@ -3,8 +3,8 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.logic.model.model.components.atomic.GUIMerger; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -19,14 +19,14 @@ public class MergerAdapter implements ComponentAdapter @Override public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, GUIMerger guiComponent, - Map logicWiresPerPin) + Map logicWiresPerPin) { - Wire output = logicWiresPerPin.get(guiComponent.getPin("O")); + CoreWire output = logicWiresPerPin.get(guiComponent.getPin("O")); ReadEnd[] inputEnds = new ReadEnd[guiComponent.logicWidth]; for (int i = 0; i < guiComponent.logicWidth; i++) { - Wire input = logicWiresPerPin.get(guiComponent.getPin("I" + (guiComponent.logicWidth - 1 - i))); - Wire.fuse(input, output, 0, i); + CoreWire input = logicWiresPerPin.get(guiComponent.getPin("I" + (guiComponent.logicWidth - 1 - i))); + CoreWire.fuse(input, output, 0, i); inputEnds[i] = input.createReadOnlyEnd(); } guiComponent.setLogicModelBinding(inputEnds, output.createReadOnlyEnd()); diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/NoLogicAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/NoLogicAdapter.java index a084ba8e..ef2375c6 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/NoLogicAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/NoLogicAdapter.java @@ -3,7 +3,7 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; +import net.mograsim.logic.core.wires.CoreWire; import net.mograsim.logic.model.model.components.GUIComponent; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -29,7 +29,7 @@ public class NoLogicAdapter implements ComponentAdapter< } @Override - public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, T guiComponent, Map logicWiresPerPin) + public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, T guiComponent, Map logicWiresPerPin) { // do nothing } diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java index 2a800461..fc981cac 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java @@ -2,11 +2,11 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; -import net.mograsim.logic.core.components.Component; +import net.mograsim.logic.core.components.CoreComponent; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularGUIGate; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -29,7 +29,7 @@ public class SimpleGateAdapter implements Co } @Override - public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, G guiComponent, Map logicWiresPerPin) + public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, G guiComponent, Map logicWiresPerPin) { ReadWriteEnd out = logicWiresPerPin.get(guiComponent.getPin("Y")).createReadWriteEnd(); @@ -44,7 +44,7 @@ public class SimpleGateAdapter implements Co public static interface ComponentConstructor { - public Component newComponent(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd[] ins); + public CoreComponent newComponent(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd[] ins); } } \ No newline at end of file diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleRectangularHardcodedGUIComponentAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleRectangularHardcodedGUIComponentAdapter.java index 8ca38c08..8634c0c2 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleRectangularHardcodedGUIComponentAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleRectangularHardcodedGUIComponentAdapter.java @@ -6,9 +6,9 @@ import java.util.concurrent.atomic.AtomicReference; import net.mograsim.logic.core.LogicObserver; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.components.atomic.SimpleRectangularHardcodedGUIComponent; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.model.wires.PinUsage; @@ -24,7 +24,7 @@ public class SimpleRectangularHardcodedGUIComponentAdapter implements ComponentA @Override public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, SimpleRectangularHardcodedGUIComponent guiComponent, - Map logicWiresPerPin) + Map logicWiresPerPin) { Map readEnds = new HashMap<>(); Map readWriteEnds = new HashMap<>(); @@ -38,7 +38,7 @@ public class SimpleRectangularHardcodedGUIComponentAdapter implements ComponentA for (Pin pin : guiComponent.getPins().values()) { - Wire wire = logicWiresPerPin.get(pin); + CoreWire wire = logicWiresPerPin.get(pin); ReadEnd end; if (pin.usage != PinUsage.INPUT) { diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SplitterAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SplitterAdapter.java index 57cad511..ab371958 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SplitterAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SplitterAdapter.java @@ -3,8 +3,8 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; import net.mograsim.logic.model.model.components.atomic.GUISplitter; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -19,14 +19,14 @@ public class SplitterAdapter implements ComponentAdapter @Override public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, GUISplitter guiComponent, - Map logicWiresPerPin) + Map logicWiresPerPin) { - Wire input = logicWiresPerPin.get(guiComponent.getPin("I")); + CoreWire input = logicWiresPerPin.get(guiComponent.getPin("I")); ReadEnd[] outputEnds = new ReadEnd[guiComponent.logicWidth]; for (int i = 0; i < guiComponent.logicWidth; i++) { - Wire output = logicWiresPerPin.get(guiComponent.getPin("O" + (guiComponent.logicWidth - 1 - i))); - Wire.fuse(input, output, i, 0); + CoreWire output = logicWiresPerPin.get(guiComponent.getPin("O" + (guiComponent.logicWidth - 1 - i))); + CoreWire.fuse(input, output, i, 0); outputEnds[i] = output.createReadOnlyEnd(); } guiComponent.setLogicModelBinding(input.createReadOnlyEnd(), outputEnds); diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/TriStateBufferAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/TriStateBufferAdapter.java index 2dadcd80..fce74726 100644 --- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/TriStateBufferAdapter.java +++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/TriStateBufferAdapter.java @@ -2,11 +2,11 @@ package net.mograsim.logic.model.modeladapter.componentadapters; import java.util.Map; -import net.mograsim.logic.core.components.TriStateBuffer; +import net.mograsim.logic.core.components.CoreTriStateBuffer; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.components.atomic.GUITriStateBuffer; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; @@ -22,11 +22,11 @@ public class TriStateBufferAdapter implements ComponentAdapter logicWiresPerPin) + Map logicWiresPerPin) { ReadEnd in = logicWiresPerPin.get(guiTsb.getPin("IN")).createReadOnlyEnd(); ReadEnd enable = logicWiresPerPin.get(guiTsb.getPin("EN")).createReadOnlyEnd(); ReadWriteEnd out = logicWiresPerPin.get(guiTsb.getPin("OUT")).createReadWriteEnd(); - new TriStateBuffer(timeline, params.gateProcessTime, in, out, enable); + new CoreTriStateBuffer(timeline, params.gateProcessTime, in, out, enable); } } diff --git a/net.mograsim.machine/src/net/mograsim/machine/Machine.java b/net.mograsim.machine/src/net/mograsim/machine/Machine.java index dc544da6..ef91fd44 100644 --- a/net.mograsim.machine/src/net/mograsim/machine/Machine.java +++ b/net.mograsim.machine/src/net/mograsim/machine/Machine.java @@ -1,6 +1,6 @@ package net.mograsim.machine; -import net.mograsim.logic.core.components.Clock; +import net.mograsim.logic.core.components.CoreClock; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.BitVector; import net.mograsim.logic.model.model.ViewModel; @@ -12,7 +12,7 @@ public interface Machine { ViewModel getModel(); - Clock getClock(); + CoreClock getClock(); BitVector getRegister(Register r); diff --git a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryAdapter.java b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryAdapter.java index ffacb74e..bf6cb4f9 100644 --- a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryAdapter.java +++ b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryAdapter.java @@ -3,9 +3,9 @@ package net.mograsim.machine.standard.memory; import java.util.Map; import net.mograsim.logic.core.timeline.Timeline; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.modeladapter.LogicModelParameters; import net.mograsim.logic.model.modeladapter.componentadapters.ComponentAdapter; @@ -22,7 +22,7 @@ public class WordAddressableMemoryAdapter implements ComponentAdapter logicWiresPerPin) + Map logicWiresPerPin) { ReadWriteEnd data = logicWiresPerPin.get(guiComponent.getDataPin()).createReadWriteEnd(); ReadEnd address = logicWiresPerPin.get(guiComponent.getAddressPin()).createReadOnlyEnd(); diff --git a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java index 4cec2b17..3c135ec4 100644 --- a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java +++ b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java @@ -2,17 +2,17 @@ package net.mograsim.machine.standard.memory; import java.util.List; -import net.mograsim.logic.core.components.BasicComponent; +import net.mograsim.logic.core.components.BasicCoreComponent; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.Bit; -import net.mograsim.logic.core.wires.Wire.ReadEnd; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadEnd; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.machine.MainMemoryDefinition; /** * A memory component that only allows access to words of a specific width */ -public class WordAddressableMemoryComponent extends BasicComponent +public class WordAddressableMemoryComponent extends BasicCoreComponent { private final WordAddressableMemory memory; private final static Bit read = Bit.ONE; diff --git a/net.mograsim.machine/test/net/mograsim/machine/standard/memory/WordAddressableMemoryTest.java b/net.mograsim.machine/test/net/mograsim/machine/standard/memory/WordAddressableMemoryTest.java index 5f50dbc9..e3566e31 100644 --- a/net.mograsim.machine/test/net/mograsim/machine/standard/memory/WordAddressableMemoryTest.java +++ b/net.mograsim.machine/test/net/mograsim/machine/standard/memory/WordAddressableMemoryTest.java @@ -10,8 +10,8 @@ import org.junit.jupiter.api.Test; import net.mograsim.logic.core.timeline.Timeline; import net.mograsim.logic.core.types.Bit; import net.mograsim.logic.core.types.BitVector; -import net.mograsim.logic.core.wires.Wire; -import net.mograsim.logic.core.wires.Wire.ReadWriteEnd; +import net.mograsim.logic.core.wires.CoreWire; +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd; import net.mograsim.machine.MainMemoryDefinition; class WordAddressableMemoryTest { @@ -21,9 +21,9 @@ class WordAddressableMemoryTest { @Test public void wordAddressableMemoryLargeTest() { - Wire rW = new Wire(t, 1, 2); - Wire data = new Wire(t, 16, 2); - Wire address = new Wire(t, 64, 2); + CoreWire rW = new CoreWire(t, 1, 2); + CoreWire data = new CoreWire(t, 16, 2); + CoreWire address = new CoreWire(t, 64, 2); ReadWriteEnd rWI = rW.createReadWriteEnd(); ReadWriteEnd dataI = data.createReadWriteEnd(); ReadWriteEnd addressI = address.createReadWriteEnd(); -- 2.17.1