From 31bc21d8c10c4e311e15256a7fa2c435810d1fe7 Mon Sep 17 00:00:00 2001 From: Daniel Kirschten Date: Mon, 7 Oct 2019 01:30:16 +0200 Subject: [PATCH] Made muSR / MSR accessible bit-wise --- .../am2900/components/am2904/Am2904MSR.json | 28 +++++++++ .../am2900/components/am2904/Am2904muSR.json | 28 +++++++++ .../am2900/components/Modeldff4_finewe.java | 57 ++++++++++++++----- 3 files changed, 99 insertions(+), 14 deletions(-) diff --git a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904MSR.json b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904MSR.json index c3b5fcfa..6eba852e 100644 --- a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904MSR.json +++ b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904MSR.json @@ -1929,6 +1929,34 @@ "delegateTarget": "dff4_finewe#0", "subStateID": "q" } + }, + "q1": { + "id": "delegating", + "params": { + "delegateTarget": "dff4_finewe#0", + "subStateID": "q1" + } + }, + "q2": { + "id": "delegating", + "params": { + "delegateTarget": "dff4_finewe#0", + "subStateID": "q2" + } + }, + "q3": { + "id": "delegating", + "params": { + "delegateTarget": "dff4_finewe#0", + "subStateID": "q3" + } + }, + "q4": { + "id": "delegating", + "params": { + "delegateTarget": "dff4_finewe#0", + "subStateID": "q4" + } } } }, diff --git a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904muSR.json b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904muSR.json index 7321c227..6aa0738b 100644 --- a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904muSR.json +++ b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2904/Am2904muSR.json @@ -1121,6 +1121,34 @@ "delegateTarget": "dff4_finewe#0", "subStateID": "q" } + }, + "q1": { + "id": "delegating", + "params": { + "delegateTarget": "dff4_finewe#0", + "subStateID": "q1" + } + }, + "q2": { + "id": "delegating", + "params": { + "delegateTarget": "dff4_finewe#0", + "subStateID": "q2" + } + }, + "q3": { + "id": "delegating", + "params": { + "delegateTarget": "dff4_finewe#0", + "subStateID": "q3" + } + }, + "q4": { + "id": "delegating", + "params": { + "delegateTarget": "dff4_finewe#0", + "subStateID": "q4" + } } } }, diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/Modeldff4_finewe.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/Modeldff4_finewe.java index d362a157..6aebcbd6 100644 --- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/Modeldff4_finewe.java +++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/Modeldff4_finewe.java @@ -46,9 +46,7 @@ public class Modeldff4_finewe extends SimpleRectangularHardcodedModelComponent @Override public Object recalculate(Object lastState, Map readEnds, Map readWriteEnds) { - Bit[] QC = (Bit[]) lastState; - if (QC == null) - QC = new Bit[] { U, U, U, U, U }; + Bit[] QC = castAndInitState(lastState); Bit CVal = readEnds.get("C").getValue(); @@ -77,29 +75,60 @@ public class Modeldff4_finewe extends SimpleRectangularHardcodedModelComponent @Override protected Object getHighLevelState(Object state, String stateID) { - switch (stateID) + Bit[] QC = castAndInitState(state); + + if ("q".equals(stateID)) + return BitVector.of(Arrays.copyOfRange(QC, 1, 5)); + if (stateID.length() == 2 && stateID.charAt(0) == 'q') { - case "q": - return state == null ? BitVector.of(U, U, U, U) : BitVector.of(Arrays.copyOfRange((Bit[]) state, 1, 5)); - default: - return super.getHighLevelState(state, stateID); + char secondChar = stateID.charAt(1); + if (secondChar >= '1' && secondChar <= '4') + return BitVector.of(QC[secondChar - '0']); } + return super.getHighLevelState(state, stateID); } @Override protected Object setHighLevelState(Object lastState, String stateID, Object newHighLevelState) { - switch (stateID) + Bit[] QC = castAndInitState(lastState); + + if ("q".equals(stateID)) { - case "q": BitVector newHighLevelStateCasted = (BitVector) newHighLevelState; if (newHighLevelStateCasted.length() != 4) throw new IllegalArgumentException("Expected BitVector of length 4, not " + newHighLevelStateCasted.length()); - System.arraycopy(newHighLevelStateCasted.getBits(), 0, lastState, 1, 4); - return lastState; - default: - return super.setHighLevelState(lastState, stateID, newHighLevelState); + System.arraycopy(newHighLevelStateCasted.getBits(), 0, QC, 1, 4); + return QC; + } + if (stateID.length() == 2 && stateID.charAt(0) == 'q') + { + char secondChar = stateID.charAt(1); + if (secondChar >= '1' && secondChar <= '4') + { + Bit newHighLevelStateCasted; + if (newHighLevelState instanceof Bit) + newHighLevelStateCasted = (Bit) newHighLevelState; + else + { + BitVector vector = (BitVector) newHighLevelState; + if (vector.length() != 1) + throw new IllegalArgumentException("Expected BitVector of length 1, not " + vector.length()); + newHighLevelStateCasted = vector.getMSBit(0); + } + QC[secondChar - '0'] = newHighLevelStateCasted; + return QC; + } } + return super.setHighLevelState(QC, stateID, newHighLevelState); + } + + private static Bit[] castAndInitState(Object state) + { + Bit[] QC = (Bit[]) state; + if (QC == null) + QC = new Bit[] { U, U, U, U, U }; + return QC; } static -- 2.17.1