From 9d37526a97dbec5434e7a2a0d7fcbf02e91a39a2 Mon Sep 17 00:00:00 2001
From: Daniel Kirschten <daniel.kirschten@gmx.de>
Date: Sun, 13 Dec 2020 21:37:23 +0100
Subject: [PATCH] Fixed a bug regarding signal widths

---
 .../net/mograsim/logic/model/verilog/model/signals/Input.java   | 2 +-
 .../net/mograsim/logic/model/verilog/model/signals/Output.java  | 2 +-
 .../net/mograsim/logic/model/verilog/model/signals/Wire.java    | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
index f80f8085..0e8669ab 100644
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
@@ -10,6 +10,6 @@ public class Input extends IOPort
 	@Override
 	public String toDeclarationVerilogCode()
 	{
-		return "input [" + getWidth() + ":0] " + getName();
+		return "input [" + (getWidth() - 1) + ":0] " + getName();
 	}
 }
diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java
index 0cea00b7..4068d27c 100644
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java
@@ -10,6 +10,6 @@ public class Output extends IOPort
 	@Override
 	public String toDeclarationVerilogCode()
 	{
-		return "output [" + getWidth() + ":0] " + getName();
+		return "output [" + (getWidth() - 1) + ":0] " + getName();
 	}
 }
diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
index 10e2a504..7e0f2cc9 100644
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
@@ -9,6 +9,6 @@ public class Wire extends Signal
 
 	public String toDeclarationVerilogCode()
 	{
-		return "wire [" + getWidth() + ":0] " + getName() + ";";
+		return "wire [" + (getWidth() - 1) + ":0] " + getName() + ";";
 	}
 }
-- 
2.17.1