From dfeebad528797afaf1889ba0bd81a248fba00420 Mon Sep 17 00:00:00 2001
From: Daniel Kirschten <daniel.kirschten@gmx.de>
Date: Mon, 6 Jan 2020 00:13:31 +0100
Subject: [PATCH] VerilogExporter: Components are now named

---
 .../src/net/mograsim/logic/model/examples/VerilogExporter.java | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
index e5c24435..70907f14 100644
--- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
+++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
@@ -423,6 +423,9 @@ public class VerilogExporter
 			result.append(COMPONENT_PREFIX);
 			String paramsString = subcomponentParams.params == JsonNull.INSTANCE ? "" : subcomponentParams.params.toString();
 			result.append(sanitizeVerilog(subcomponentID + paramsString));
+			result.append(' ');
+			// abuse the pinIdentifierGenerator for making these unique
+			result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
 			result.append(" (");
 			for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
 			{
-- 
2.17.1