From e52b37182bb631540ebfe9e6253843ec5b0828a6 Mon Sep 17 00:00:00 2001
From: Daniel Kirschten <daniel.kirschten@gmx.de>
Date: Mon, 30 Mar 2020 18:37:13 +0200
Subject: [PATCH] Implemented the YR output of the Am2910InstrPLA in gates; w/o
 layout

---
 .../components/am2910/Am2910InstrPLA.json     | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json
index 9c508b9c..9ff367cf 100644
--- a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json
+++ b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json
@@ -681,6 +681,15 @@
         },
         "params": 1
       },
+      {
+        "id": "NandGate",
+        "name": "NandGate#61",
+        "pos": {
+          "x": 335.0,
+          "y": 105.0
+        },
+        "params": 1
+      },
       {
         "id": "Splitter",
         "name": "Splitter#0",
@@ -1305,6 +1314,14 @@
           "x": 435.0,
           "y": 290.0
         }
+      },
+      {
+        "id": "and",
+        "name": "and#17",
+        "pos": {
+          "x": 365.0,
+          "y": 120.0
+        }
       }
     ],
     "wires": [
@@ -4494,6 +4511,66 @@
         },
         "name": "unnamedWire#218",
         "path": []
+      },
+      {
+        "pin1": {
+          "compName": "NandGate#40",
+          "pinName": "Y"
+        },
+        "pin2": {
+          "compName": "NandGate#61",
+          "pinName": "A"
+        },
+        "name": "unnamedWire#219",
+        "path": []
+      },
+      {
+        "pin1": {
+          "compName": "WireCrossPoint#1",
+          "pinName": ""
+        },
+        "pin2": {
+          "compName": "and#17",
+          "pinName": "B"
+        },
+        "name": "unnamedWire#220",
+        "path": []
+      },
+      {
+        "pin1": {
+          "compName": "and#17",
+          "pinName": "Y"
+        },
+        "pin2": {
+          "compName": "_submodelinterface",
+          "pinName": "YR"
+        },
+        "name": "unnamedWire#221",
+        "path": []
+      },
+      {
+        "pin1": {
+          "compName": "NandGate#61",
+          "pinName": "B"
+        },
+        "pin2": {
+          "compName": "NandGate#40",
+          "pinName": "Y"
+        },
+        "name": "unnamedWire#222",
+        "path": []
+      },
+      {
+        "pin1": {
+          "compName": "NandGate#61",
+          "pinName": "Y"
+        },
+        "pin2": {
+          "compName": "and#17",
+          "pinName": "A"
+        },
+        "name": "unnamedWire#223",
+        "path": []
       }
     ],
     "version": "0.1.1"
-- 
2.17.1