From e651a2134243edc61e046c79d3b20b96462f47cf Mon Sep 17 00:00:00 2001 From: Daniel Kirschten Date: Mon, 14 Dec 2020 01:41:55 +0100 Subject: [PATCH] Interface pins are now sorted --- .../verilog/converter/ModelComponentToVerilogConverter.java | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogConverter.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogConverter.java index 00d777b0..6c12a07b 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogConverter.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogConverter.java @@ -2,6 +2,7 @@ package net.mograsim.logic.model.verilog.converter; import java.util.ArrayList; import java.util.Collection; +import java.util.Comparator; import java.util.HashMap; import java.util.HashSet; import java.util.List; @@ -89,7 +90,8 @@ public class ModelComponentToVerilogConverter Map> pinMapping = new HashMap<>(); for (Type t : Type.values()) pinMapping.put(t, new HashMap<>()); - for (Pin modelPin : modelComponent.getPins().values()) + for (Pin modelPin : (Iterable) () -> modelComponent.getPins().values().stream().sorted(Comparator.comparing(p -> p.name)) + .iterator()) for (int bit = 0; bit < modelPin.logicWidth; bit++) { PinNameBit pinbit = new PinNameBit(modelPin.name, bit); @@ -111,7 +113,7 @@ public class ModelComponentToVerilogConverter Map pinMappingCorrectType = pinMapping.get(type); pinMappingCorrectType.computeIfAbsent(connectedPins.find(pinbit), p -> { - String portID = ioPortIDGen.generateID(p.getName() + "_" + p.getBit() + "_" + suffix); + String portID = ioPortIDGen.generateID(pinbit.getName() + "_" + pinbit.getBit() + "_" + suffix); IOPort ioPort = constr.apply(portID, 2); int index = ioPorts.size(); ioPorts.add(ioPort); -- 2.17.1