Corrected RAM control signal timing
authorDaniel Kirschten <daniel.kirschten@gmx.de>
Tue, 17 Sep 2019 16:02:40 +0000 (18:02 +0200)
committerDaniel Kirschten <daniel.kirschten@gmx.de>
Tue, 17 Sep 2019 16:03:12 +0000 (18:03 +0200)
commit1234597eaff5990ecc51d90856786702cc33f52e
treeef3576f58cb83dbd96879c26886410fe636b0ec8
parent8715b7b869a0786adb2a853770d23fa9352d9072
Corrected RAM control signal timing
plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/Am2900.json