Refactored Wire and finally renamed length to width
authorChristian Femers <femers@in.tum.de>
Mon, 26 Aug 2019 01:03:45 +0000 (03:03 +0200)
committerChristian Femers <femers@in.tum.de>
Mon, 26 Aug 2019 01:03:45 +0000 (03:03 +0200)
commit3e6ac3d7fd389191d02c1c6982fbf093421ce4f2
treef1329eaa1250e81efcee91f0a3b952e659cdd58d
parent2e7dc40f788b00146f2d0805fecd9d23adbda363
Refactored Wire and finally renamed length to width

Note: since this change was prolonged for some time, so it needed to be changed in a lot of places. The reason for the renaming is the confusability with the length of a (e.g. physical) wire. But it is more precise to call it (bit-) width, since the length of a BitVector passing through the wire becomes its width. (This seems to be similar named in Verilog)
13 files changed:
net.mograsim.logic.core/src/net/mograsim/logic/core/components/Connector.java
net.mograsim.logic.core/src/net/mograsim/logic/core/components/Demux.java
net.mograsim.logic.core/src/net/mograsim/logic/core/components/ManualSwitch.java
net.mograsim.logic.core/src/net/mograsim/logic/core/components/Merger.java
net.mograsim.logic.core/src/net/mograsim/logic/core/components/Mux.java
net.mograsim.logic.core/src/net/mograsim/logic/core/components/Splitter.java
net.mograsim.logic.core/src/net/mograsim/logic/core/components/TriStateBuffer.java
net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java
net.mograsim.logic.core/src/net/mograsim/logic/core/wires/Wire.java
net.mograsim.logic.core/test/net/mograsim/logic/core/tests/ComponentTest.java
net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2904/GUIAm2904RegCTInstrDecode.java
net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/ViewLogicModelAdapter.java
net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java