Added gate/wire delay in SubmodelComponentTestbench
authorDaniel Kirschten <daniel.kirschten@gmx.de>
Tue, 4 Jun 2019 13:32:13 +0000 (15:32 +0200)
committerDaniel Kirschten <daniel.kirschten@gmx.de>
Tue, 4 Jun 2019 13:32:13 +0000 (15:32 +0200)
commit8cb74696d25006bba0a24954184a8c7214c07c11
tree6178e3cfcda6b286656a4012c7682e99cadaf52e
parent7b0da7328f81fd64f3f674e33ea030e896759a58
Added gate/wire delay in SubmodelComponentTestbench
net.mograsim.logic.ui/src/net/mograsim/logic/ui/examples/SubmodelComponentTestbench.java