Generated Verilog now has a RST "pin"
authorDaniel Kirschten <daniel.kirschten@gmx.de>
Tue, 4 Feb 2020 10:54:19 +0000 (11:54 +0100)
committerDaniel Kirschten <daniel.kirschten@gmx.de>
Tue, 4 Feb 2020 10:54:19 +0000 (11:54 +0100)
commitb1933553071bd1f24890a6d4d6bd91f555db69c2
treeb768b4caa7cf96c6802e4908475cbcc21697986d
parent85135c0930920ee46588238f55105521a5edaff5
Generated Verilog now has a RST "pin"
plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java