Fixed ModelClock's high level state:
authorDaniel Kirschten <daniel.kirschten@gmx.de>
Wed, 2 Oct 2019 14:02:42 +0000 (16:02 +0200)
committerDaniel Kirschten <daniel.kirschten@gmx.de>
Wed, 2 Oct 2019 14:02:42 +0000 (16:02 +0200)
commitf1933b06b5fe800902131e4dc34f002ac3fa17f0
treeaa837f22e985ea68a70710775b49d01fe3af363c
parent28bd84e7a569624922c8fd96df511b7e6581315a
Fixed ModelClock's high level state:

Was inverted when read before wireTravelTime elapsed
plugins/net.mograsim.logic.core/src/net/mograsim/logic/core/components/CoreClock.java
plugins/net.mograsim.logic.model/src/net/mograsim/logic/model/model/components/atomic/ModelClock.java