From: Daniel Kirschten <daniel.kirschten@gmx.de>
Date: Mon, 15 Mar 2021 15:38:48 +0000 (+0100)
Subject: Handing through rst and clk signals (still very ugly)
X-Git-Url: https://mograsim.net/gitweb/?p=Mograsim.git;a=commitdiff_plain;h=253f4e92e8a8b644ef5fa2343adc3088954822ee

Handing through rst and clk signals (still very ugly)
---

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java
index a7a9de29..3dead220 100644
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java
@@ -58,7 +58,10 @@ public class VerilogComponentImplementation
 		StringBuilder sb = new StringBuilder();
 
 		sb.append("module " + declaration.getID());
-		sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode).collect(Collectors.joining(", ", "(", ")")));
+		// TODO handle rst / clk more cleanly.
+		// Also in CompenentReference
+		sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode)
+				.collect(Collectors.joining(", ", "(input rst,input clk,", ")")));
 		sb.append(";\n\n");
 
 		for (Statement statement : statements)
diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java
index dcce7606..94a214e6 100644
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java
@@ -59,7 +59,8 @@ public class ComponentReference extends Statement
 		StringBuilder sb = new StringBuilder();
 
 		sb.append(referencedComponent.getID() + " " + name);
-		sb.append(arguments.stream().map(Expression::toVerilogCode).collect(Collectors.joining(", ", "(", ")")));
+		// TODO handle rst / clk more cleanly; see VerilogCompenentImplementation
+		sb.append(arguments.stream().map(Expression::toVerilogCode).collect(Collectors.joining(", ", "(rst,clk,", ")")));
 		sb.append(";");
 
 		return sb.toString();